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Device Initialization by ROM Code
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The following sections describe the supported booting device types.
For more information about the GPMC module, see
, Memory Subsystem.
26.4.7.3 XIP Memory
The ROM code can boot directly from XIP booting devices, such as NOR flash memories, that have the
following characteristics:
•
The GPMC is the communication interface.
•
Memories up to 2 Gb (256MB) can be connected.
•
x16 data bus width only
•
Asynchronous protocol and address/data multiplexed mode
•
The GPMC clock is 48 MHz.
•
The booting device is connected to CS0 mapped to address 0x0800 0000.
•
The wait pin signal gpmc_wait0 is monitored according to the sys_boot configuration pins.
Depending on the sys_boot option, the GPMC can be configured to use the wait signal connected to the
gpmc_wait0 pin. Wait pin polarity is set to stall accessing memory when gpmc_wait0 is low. Wait
monitoring is used with memories that require a long time for initialization after reset, or that must pause
while reading data. An example of such memory is DiskOnChip.
For an XIP memory booting, no user intervention is needed; the following steps are described for
debugging. Only the CH, which is not mandatory, lets the user change clock settings and GPMC
parameters. Failure in CH copying causes a return to the main booting procedure, which selects the next
booting device.
Booting from an XIP booting device consists of the following steps:
1. Configure the GPMC for XIP booting device access.
2. Verify that the CH is present at address 0x0800 0000. If it is, copy the entire sector (512 B) to internal
RAM and execute the CH.
3. Set the image location:
•
0x0800 0000 if the CH is not found
•
0x0800 0200 if the CH (512 bits) is found
4. Verify that a bootable image is at the image location.
5. Execute the image if it is found.
6. If the image is not found, return from XIP booting to the main booting loop.
26.4.7.3.1 GPMC Initialization
describes the timing settings of GPMC set for XIP and other address-data accessible booting
devices, like DiskOnChip or OneNAND/Flex-OneNAND.
is included for debug information.
Table 26-30. XIP Timing Parameters
Parameter
Value [Clock Cycles] Register Initialization (where i = 0...7)
Reset Value
Write cycle time
17
The GPMC_CONFIG5_i[12:8] WRCYCLETIME bit field is set
0x11
to 0x11.
Read cycle time
17
The GPMC_CONFIG5_i[4:0] RDCYCLETIME bit field is set to
0x11
0x11.
CS low time
1
The GPMC_CONFIG2_i[3:0] CSONTIME bit field is set to 0x1.
0x1
CS high time
16
The GPMC_CONFIG2_i[12:8] CSRDOFFTIME bit field is set
0x10
to 0x10.
ADV low time
1
The GPMC_CONFIG3_i[3:0] ADVONTIME bit field is set to
0x1
0x1.
ADV high time
2
The GPMC_CONFIG3_i[12:8] ADVRDOFFTIME bit field is set
0x2
to 0x2.
OE low time
3
The GPMC_CONFIG4_i[3:0] OEONTIME bit field is set to 0x3.
0x3
3544
Initialization
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
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