Public Version
MMU Register Manual
www.ti.com
15.5.2 MMU Register Description
Table 15-10. MMU_REVISION
Address Offset
0x000
Physical address
0x480B D400
Instance
MMU1 (Camera ISP MMU)
0x5D00 0000
MMU2 (IVA2.2 MMU)
Description
This register contains the IP revision code.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
REV
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Reads return 0.
R
0x000000
7:0
REV
IP revision
R
See
(1)
[7:4]: Major revision
[3:0]: Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
(1)
TI internal data
Table 15-11. Register Call Summary for Register MMU_REVISION
MMU Register Manual
•
Table 15-12. MMU_SYSCONFIG
Address Offset
0x010
Physical address
0x480B D410
Instance
MMU1 (Camera ISP MMU)
0x5D00 0010
MMU2 (IVA2.2 MMU)
Description
This register contains the various parameters of the interconnect interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
AUTOIDLE
IDLEMODE
SOFTRESET
CLOCK
ACTIVITY
Bits
Field Name
Description
Type
Reset
31:10
Reserved
Reads return 0. Write 0s for future compatibility.
R
0x000000
9:8
CLOCKACTIVITY
Clock activity during wake-up mode
R
0x0
Read 0x0: Functional and interconnect clocks can be switched off.
Read 0x1, 0x2, 0x3: never happens.
Write 0s for future compatibility.
7:5
Reserved
Reads return 0. Write 0s for future compatibility.
R
0x0
4:3
IDLEMODE
Idle mode
RW
0x0
0x0:
Force idle. Idle request is acknowledged unconditionally.
0x1:
No idle. Idle request is never acknowledged.
0x2:
Smart idle. Acknowledgement to an idle request is given based on
the internal activity of the module.
0x3:
Reserved - Do not use
2
Reserved
Reads return 0. Write 0s for future compatibility.
R
0
2688
Memory Management Units
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...