Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1069 / 3738

Public Version
www.ti.com
IVA2.2 Subsystem Register Manual
5.5.13.2 iLF Register Descriptions
Table 5-752. iLF_REVISION
Address Offset 0x0000 0000
Physical Address 0x000A 1000 Instance iLF
Description This register contains the iLF revision code
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REV
Bits Field Name Description Type Reset
31:8 RESERVED Read returns 0 R 0x000000
7:0 REV iLF Revision R See
(1)
[3:0] Minor Revision
[7:4] Major Revision
(1)
TI internal data
Table 5-753. Register Call Summary for Register iLF_REVISION
IVA2.2 Subsystem Register Manual
• iLF Register Mapping Summary : [0]
Table 5-754. iLF_SYSCONFIG
Address Offset 0x0000 0010
Physical Address 0x000A 1010 Instance iLF
Description This register allows controlling various parameters of the OCP interface
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTOIDLE
RESERVED RESERVED
SIDLEMODE
SOFTRESET
CLOCKACTIVITY
Bits Field Name Description Type Reset
31:9 RESERVED Read returns 0. R 0x0
8 CLOCKACTIVITY Clock activity during wake up mode period. R 0x0
0 - OCP clock can be switched-off.
7:5 RESERVED read returns 0. R 0x0
4:3 SIDLEMODE Slave interface power management, req/ack control R 0x2
"10" = Smart-idle. Acknowledgement to an idle request is given
based on the internal activity of iME
2 RESERVED read returns 0. R 0x0
1 SOFTRESET Software reset. Set this bit to 1 to trigger the iME reset. RW 0x0
The bit is automatically reset by the hardware. During reads, it
always returns 0.
0 AUTOIDLE Internal OCP clock gating strategy: RW 0x1
0: OCP clock is free running
1: Automatic OCP clock-gating strategy is applied based on the
OCP interface activity
1069 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated