Texas Instruments OMAP36 Series, Техническое справочное руководство

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UART/IrDA/CIR Functional Description
19.4.4.1.3.5 Error Detection
When the UARTi. LSR_REG register is read, UARTi. LSR_REG [4:2] reflects the error bits (BI: break
condition, FE: framing error, PE: parity error) of the character at the top of the RX FIFO (next character to
be read). Therefore, reading the UARTi.
LSR_REG register and then reading the UARTi. RHR_REG
register identifies errors in a character.
Reading the UARTi. RHR_REG register updates the BI, FE, and PE bits (see Table 19-33 for the UART
mode interrupts).
The UARTi. LSR_REG [7] RX_FIFO_STS bit is set when there is an error in the RX FIFO and is cleared
only when no errors remain in the RX FIFO.
NOTE: Reading UARTi. LSR_REG does not cause an increment of the RX FIFO read pointer. The
RX FIFO read pointer is incremented by reading UARTi. RHR_REG .
Reading UARTi. LSR_REG clears the OE bit if it is set (see Table 19-33 for the UART mode interrupts).
19.4.4.1.3.6 Overrun During Receive
Overrun during receive occurs if the RX state-machine tries to write data into the RX FIFO when it is
already full. When overrun occurs, the device interrupts the MPU with UARTi.
IIR_REG [5:1] IT_TYPE =
0x3 (receiver line status error) and discards the remaining portion of the frame.
Overrun also causes an internal flag to be set, which disables further reception. Before the next frame can
be received, the system (MPU) must:
•
Reset the RX FIFO
• Read the UARTi. RESUME_REG register (which clears the internal flag)
19.4.4.1.3.7 Time-Out and Break Conditions
19.4.4.1.3.7.1 Time-Out Counter
An RX idle condition is detected when the receiver line (uarti_rx) is high for a time equivalent to 4x
programmed word 12 bits. uarti_rx is sampled midway through each bit.
For sleep mode, the counter is reset when there is activity on uarti_rx.
For the time-out interrupt, the counter counts only when there is data in the RX FIFO, and the count is
reset when there is activity on uarti_rx or when the UARTi.
RHR_REG is read.
19.4.4.1.3.7.2 Break Condition
When a break condition occurs, uarti_tx is pulled low. A break condition is activated by setting the
UARTi.
LCR_REG [6] BREAK_EN bit. The break condition is not aligned on word stream (that is, a break
condition can occur in the middle of a character). The only way to send a break condition on a full
character is as follows:
1. Reset the transmit FIFO (if enabled).
2. Wait for the transmit shift register to empty (UARTi.
LSR_REG [6] TX_SR_E = 1).
3. Take a guard time according to stop-bit definition.
4. Set the BREAK_EN bit to 1.
The break condition is asserted while the BREAK_EN bit is set to 1.
The time-out counter and break condition apply only to UART modem operation and not to IrDA/CIR mode
operation.
19.4.4.1.4 UART Mode Interrupt Management
The UART mode includes seven possible interrupts prioritized to six levels.
2909 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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