Texas Instruments OMAP36 Series, Техническое справочное руководство

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McBSP Basic Programming Model
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The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes a
counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as the
input for the second and third stages of the divider.
CLKG has a frequency equal to 1/(1) of SRG input clock. Thus, the sample generator input
clock frequency is divided by a value between 1 and 256. The CLKG duty cycle is 50%.
21.5.1.5.2.4.4 Set the SRG Clock Synchronization Mode
McBSPi. MCBSPLP_SRGR2_REG [15] GSYNC bit is used to set the SRG clock synchronization mode.
For more information about the clock synchronization feature, see Section 21.4.3 .
21.5.1.5.2.4.5 Set the SRG Clock Mode (Choose an Input Clock)
McBSPi. MCBSPLP_PCR_REG [7] SCLKME bit and McBSPi. MCBSPLP_SRGR2_REG [13] CLKSM bit are
used to set the SRG clock mode.
The SRG can produce a clock signal (CLKG) for use by the receiver, the transmitter, or both, but CLKG is
derived from an input clock.
For further details about the clock synchronization feature, see Section 21.4.3 .
21.5.1.5.2.4.6 Set the SRG Input Clock Polarity
McBSPi. MCBSPLP_SRGR2_REG [14] CLKSP bit, McBSPi. MCBSPLP_PCR_REG [1] CLKXP bit and
McBSPi. MCBSPLP_PCR_REG [0] CLKRP bit are used to set the SRG input clock polarity.
The SRG can produce a clock signal (CLKG) and a frame-synchronization signal (FSG) for use by the
receiver, the transmitter, or both. To produce CLKG and FSG, the SRG must be driven by an input clock
signal derived from the McBSP_FCLK clock or from an external clock on the mcbsp_clks, mcbsp_clkx, or
mcbsp_clkr pin. If you use a pin, choose a polarity for that pin by using the appropriate polarity bit (CLKSP
for the mcbsp_clks pin, CLKXP for the mcbsp_clkx pin, CLKRP for the mcbsp_clkr pin). The polarity
determines whether the rising or falling edge of the input clock generates transitions on CLKG and FSG.
21.5.1.6 Transmitter Configuration
To configure the McBSP transmitter, perform the following procedure:
1. Place the McBSP transmitter in reset
2. Program the McBSP registers for the desired transmitter operation
3. Take the transmitter out of reset
These 3 steps are described in more details in the sub-sections below.
21.5.1.6.1 Resetting (Step 1) and Enabling (Step 3) the Transmitter
The first step of the transmitter configuration procedure is to reset the transmitter, and the last step is to
enable the transmitter (to take it out of reset).
The serial port can be reset in the following two ways:
1. A global reset places the receiver, transmitter, and SRG in reset. When the device reset is removed,
McBSPi. MCBSPLP_SPCR2_REG [6] GRST, McBSPi. MCBSPLP_SPCR2_REG [7] FRST,
McBSPi. MCBSPLP_SPCR1_REG [0] RRST and McBSPi. MCBSPLP_SPCR2_REG [0] XRST bits = 0,
which keeps the entire serial port in the reset state.
2. The serial port receiver can be reset directly using the McBSPi. MCBSPLP_SPCR2_REG [0] XRST bit.
If the SRG needs to be used, SRG must be reset directly using the
McBSPi.
MCBSPLP_SPCR2_REG [6] GRST bit. Similar operation with the Frame Synchronization
Generator also requires using the McBSPi. MCBSPLP_SPCR2_REG [7] FRST bit when the frame-sync
signal must be generated.
To enable the transmitter, the preceding bits, cleared to 0, must be set to 1.
3142 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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