Texas Instruments OMAP36 Series, Техническое справочное руководство

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High-Speed USB OTG Controller
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• Set the USBOTG.POWER[2] RESUME bit to 1.
• Write 0 to the USBOTG. OTG_FORCESTDBY [0] ENABLEFORCE bit.
OR
• RESET interrupt is generated by the high-speed USB controller.
• Write 0 to the USBOTG. OTG_FORCESTDBY [0] ENABLEFORCE bit.
When MSTANDBY is deasserted as a consequence of the previous register access, the module waits
for MWAIT deassertion before a DMA transfer is started.
• No standby
The high-speed USB controller is configured in no-standby mode (USBOTG.
OTG_SYSCONFIG [13:12]
MIDLEMODE field = 0x1). The module never enters standby mode (that is, MSTANDBY is never
asserted).
Table 22-4 describes the high-speed USB master interface power management modes.
Table 22-4. High-Speed USB Master Interface Power Management Modes
Power Management Mode Requested by the PRCM USBOTG. OTG_SYSCONFIG [13:12] MIDLEMODE Field
Force-standby 0x0
No-standby 0x1
Smart-standby 0x2
Reserved 0x3
Slave Interface Power Management
The high-speed USB controller can be configured through the USBOTG. OTG_SYSCONFIG [4:3]
SIDLEMODE field as one of the following acknowledgment modes:
• Smart-Idle Mode
When the high-speed USB controller receives an IDLE request from the PRCM module:
– The interface clock USBHS_ICLK is disabled (PRCM register bit PRCM.CM_ICLKEN1_CORE[4]
set to 0) or under automatic control (PRCM register bits PRCM.CM_ICLKEN1_CORE[4] and
PRCM.CM_AUTOIDLE1_CORE[4] both set to 1)
– L4 interface clock idle transitions:
Configured in smart-idle mode (USBOTG.
OTG_SYSCONFIG [4:3] SIDLEMODE field = 0x2), the
high-speed USB controller checks for no ongoing activity. The idle acknowledge then is asserted
and the module waits for active system clock gating by the PRCM module (this occurs only when all
peripherals supplied by the same L3 clock domain are also ready for idle).
Once in idle mode (when the PRCM module gates the interface clock), the module has no activity, the
interface clock paths are gated, no interrupt request can be generated, and the module is ready to
issue a wake-up request. If a wake-up condition occurs, the high-speed USB controller exits from idle
mode if the USBOTG.
OTG_SYSCONFIG [2] ENABLEWAKEUP bit is set to 1 (wake-up capability
enabled) and the PRCM register bit PRCM.PM_WKEN1_CORE[4] is also set to 1.
• Force-Idle Mode
When the high-speed USB controller receives an IDLE request from the PRCM module:
– The interface clock USBHS_ICLK is disabled (PRCM register bit PRCM.CM_ICLKEN1_CORE[4]
set to 0) or under automatic control (PRCM register bits PRCM.CM_ICLKEN1_CORE[4] and
PRCM.CM_AUTOIDLE1_CORE[4] both set to 1)
– The L4 interface clock idle transitions:
Configured in force-idle mode (USBOTG.
OTG_SYSCONFIG [4:3] SIDLEMODE field = 0x0), the
high-speed USB controller waits unconditionally for active system clock gating by the PRCM
module (this occurs only when all peripherals supplied by the same L3 clock domain are also ready
for idle).
Once in idle mode (when the PRCM module gates the interface clock), the module has no activity, the
interface clock paths are gated, no interrupt request can be generated, and the wake-up feature is
totally inhibited.
• No-Idle Mode
When the high-speed USB controller receives an IDLE request from the PRCM module:
3218 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
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