Public Version
www.ti.com
PRCM Functional Description
3.5.3.5.3 External Output Clock1 (sys_clkout1) Control
The sys_clkout1 clock is active if the oscillator clock (OSC_SYS_CLK) is active (stable) and an external
system clock request is active. It can be gated by programming the PRCM.
CLKOUT_EN bit. The polarity of the sys_clkout1 signal, when the clock is gated, is controllable by
programming the PRCM.
[2] CLKOUT_POL bit.
When the device is in standby mode, SYS_CLK and sys_clkout1 are disabled. in this case, reactivation of
sys_clkout1 depends on the oscillator mode:
•
Oscillator in active mode (sys_boot6 is 0): The sys_clkout1 clock can be reactivated (after oscillator
stabilization), provided its gating was enabled by programming the PRCM.
[7]
CLKOUT_EN bit and asserting an external clock request. This activation does not generate a device
wake-up event; an external clock request activates only the internal SYS_CLK oscillator and
sys_clkout1.
•
Oscillator in bypass mode (sys_boot6 is 1): The sys_clkout1 clock can be reactivated only after the
device wakes up (on any wake-up event) and SYS_CLK is active. When the device is active,
SYS_CLK is running and sys_clkout1 is enabled as soon as requested by software.
3.5.3.5.4 External Output Clock2 (sys_clkout2) Control
A second output clock, sys_clkout2, is generated with a frequency that can be the source-clock frequency
divided by 1, 2, 4, 8, or 16. Its source clock can be CORE_CLK, CM_SYS_CLK, 96 MHz, or 54 MHz.
Unlike sys_clkout1, this second external clock is not active when the device is in off power mode. Also,
the selected source clock must be enabled by software. Enabling sys_clkout2 does not automatically
request the required source clock. The polarity of the sys_clkout2 signal, when the clock is gated, is
controllable by programming the PRCM.
[0] CLKOUT2_POL bit.
3.5.3.6
DPLL Control
The PRCM module allows the configuration of the output clock frequencies of the DPLLs by setting their
multipliers and dividers. It also allows control of the operating mode of the DPLLs and automatic
recalibration mode.
3.5.3.6.1 DPLL Multiplier and Divider Factors
DPLL clock outputs are set by programming the corresponding multiplier and divider factors M, N, M2, M3,
M4, M5, and M6.
lists the register bit fields for configuration of the multiplier and divider factors
for the DPLLs.
Table 3-38. DPLL Multiplier and Divider Factors
DPLL1
DPLL2
DPLL3
DPLL4
DPLL5
M
PRCM.CM_CLKSEL1_
PRCM. CM_CLKSEL1_PLL_
PRCM.CM_CLKSEL1_
PRCM.CM_CLKSEL2_
PRCM.CM_CLKSEL4_
PLL_MPU[18:8] MPU_
IVA2[18:8] IVA2_
PLL[26:16] CORE_DPLL_MULT
PLL[18:8] PERIPH_
PLL[18:8] PERIPH2_
DPLL_MULT
DPLL_MULT
DPLL_MULT
DPLL_MULT
N
PRCM.CM_CLKSEL1_
PRCM. CM_CLKSEL1_PLL_
PRCM.CM_CLKSEL1_
PRCM.CM_CLKSEL2_
PRCM.CM_CLKSEL4_
PLL_MPU[6:0] MPU_
IVA2[6:0] IVA2_DPLL_DIV
PLL[14:8] CORE_DPLL_DIV
PLL[6:0] PERIPH_
PLL[6:0] PERIPH2_
DPLL_DIV
DPLL_DIV
DPLL_DIV
M2
PRCM.CM_CLKSEL2_
PRCM. CM_CLKSEL2_PLL_
PRCM.CM_CLKSEL1_
PRCM.CM_CLKSEL3_
PRCM.CM_CLKSEL5_
PLL_MPU[4:0] MPU_
IVA2[4:0] IVA2_DPLL_
PLL[31:27] CORE_DPLL_
PLL[4:0] DIV_96M
PLL[4:0] DIV_120M
DPLL_CLKOUT_DIV
CLKOUT_DIV
CLKOUT_DIV
M3
Not used
Not used
PRCM.CM_CLKSEL1_
PRCM.CM_CLKSEL_
Not used
EMU[21:16] DIV_DPLL3
DSS[13:8] CLKSEL_TV
M4
Not used
Not used
Not used
PRCM.CM_CLKSEL_
Not used
DSS[5:0] CLKSEL_DSS1
M5
Not used
Not used
Not used
PRCM.CM_CLKSEL_
Not used
CAM[5:0] CLKSEL_CAM
M6
Not used
Not used
Not used
PRCM.CM_CLKSEL1_
Not used
EMU[29:24] DIV_DPLL4
3.5.3.6.2 DPLL Modes
DPLL supports several power modes (see
). Each mode results in a tradeoff between power
savings and relock time.
329
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...