camisp-022
CAM.TCTRL_CTRL[4:0]
DIVA
CSI2_96M_FCLK
CAM_L4_ICLK
CAM_MCLK
cam_pclk
Divider
1,...,30
CAM.TCTRL_CTRL[9:5]
DIVB
cam_xclka
cam_xclkb
CSI2_96M_FCLK
CAM_ICLK
cam_pclk
Divider
1,...,30
CM_FCLKEN_CAM[1]
EN_CSI2
CAM_L3_ICLK
CAM_FCLK
CM_ICLKEN_CAM[0]
EN_CAM
CM_ICLKEN_CAM[0]
EN_CAM
CM_FCLKEN_CAM[0]
EN_CAM
Camera ISP
Public Version
Camera ISP Integration
www.ti.com
•
CSI2 Serial interface clock domain
•
CSI2 byte clock domain, whitch frequency depends on the image sensor type and size, its frame rate
and its blanking period. The clock is generated from the bit-clock from the sensor and converted into
byte clock.
•
Parallel interface clock domain. This frequency depends on the imaging sensor type and size, its frame
rate and its blanking time. The functional clock is required to be at least 2x faster than the pixel clock
when the bridge is disabled and a least equal when it is enabled.
•
Slave interface clock domain, from L4 interconnect
6.3.1.1.1 Camera ISP Clock Tree
shows the clock tree for the camera ISP module.
Figure 6-51. Camera ISP Clock Tree Diagram
6.3.1.1.2 Camera ISP Clock Descriptions
describes the camera ISP clocks.
Table 6-12. Camera ISP Clock Descriptions
Signal Name
IO
Description
CAM_FCLK
Input
Functional clock (L3 interconnect clock domain) Functional clock
domain.
CAM_ICLK
Input
Interface clock (L4 interconnect clock domain) Interface clock
domain.
CAM_MCLK
(1)
Input
Internal clock from PRCM at 216 MHz. The CAM_MCLK is used by
the clock generator to generate cam_xclka and cam_xclkb. It is also
used by the control Signal generator to generate cam_shutter,
cam_strobe, and cam_global_reset. For more information, see
, Camera ISP Timing Control.
cam_xclka
Output
External clock for the image-sensor module. For serial or parallel
sensor.
(1)
The CAM_MCLK frequency can be less than, or equal to 216 MHz.
1140Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...