Texas Instruments OMAP36 Series, Техническое справочное руководство

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High-Speed USB Host Subsystem
CAUTION
These bits show the port status as connected after power on even though no
USB device is connected. The USB host controller has operational status
registers (for example, USBHOST.
HCRHPORTSTATUS_1 for OHCI port 1)
that indicate the correct port connect status. The USB driver software must
read these status bits and check whether or not a port is connected. If the port
is
not connected, the USB driver software must reprogram the
USBHOST. UHH_HOSTCONFIG bits to indicate the correct port connect status.
22.2.4.1.6 Save and Restore
The save-and-restore (SAR) mechanism can extract the hardware context of the high-speed USB host
controller (after all USB activity has been suspended) before switching off (=save), save it to an external
always-on memory, and reinject it later after the module has been switched on again and reset (=restore)
seamlessly for the USB. Part of that context is composed of the register fields described in the current
chapter. The rest of the context is composed of the "buried" flip-flops and memories (not accessible by
software) like finite state-machine (FSM) states, buffer contents, and miscellaneous random logic bits.
The PRCM.PM_PWSTCTRL_USBHOSTE[4] SAVEANDRESTORE bit enables the SAR mechanism for
the high-speed USB host controller (see
Chapter 3 , Power, Reset, and Clock Management). When set,
the PRCM module initiates the save and/or the restore sequences at the appropriate time. When not set,
the USB host is treated as a standard module, and the save/restore sequences do not occur.
22.2.4.1.7 L3 Burst Control
To avoid buffer underflow, bursts must be enabled by writing 0x7 in the
USBHOST.
UHH_HOSTCONFIG [4:2] bit field and by setting the USBHOST. UHH_HOSTCONFIG [5]
ENA_INCR_ALIGN bit to 1.
22.2.4.2 USBTLL Module Functionality
The USBTLL module implements a TLL compatible with a number of USB standard interface protocols.
Once the interface protocol has been selected during an initial configuration phase, USB operation should
take place seamlessly (that is, as if actual transceivers were present). To ensure maximum compatibility,
as many features as possible have been included, as described in the rest of this document. The basic
principle is that all the software "handles" should be available and behave in a proper way, even if there is
no actual functionality underneath.
The USBTLL module is integrated with the high-speed USB host controller in the device. The transceiver
interfaces (UTMI ports) between the high-speed USB host controller and the USBTLL module are on-chip
and remain invisible. The other transceiver interfaces go off-chip, where they can be connected to the
other controllers (for example, peripherals) on another IC.
22.2.4.2.1 Channels and Ports
Following the same convention than UTMI and ULPI, the current specification is consistently PHY-centric
(that is, directions are always given with respect to the transceiver emulated here by the TLL), and not
with respect to the link controller: An "input" goes from the link controller to the TLL (transceiver emulator)
(that is, it is an input for the USBTLL module. Reciprocally, an "output" goes from TLL (transceiver) to the
link controller (that is, it is an output for the USBTLL module).
By convention, the local link controller is the controller integrated on the same IC as the USBTLL module:
This is the high-speed USB host controller in the device. The remote link controller is the other controller,
located off-chip (that is, on another IC). One controller is always the USB host, the other the USB
peripheral, and they communicate through the USBTLL module.
A channel is defined as a independent USB path through the USBTLL module, which always converts the
UTMI+ transceiver interface protocol coming from the local link controller (the high-speed USB host
controller in the device). The number of channels of the USBTLL module is three in the device.
3273 SWPU177N – December 2009 – Revised November 2010 High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated