Public Version
McSPI Integration
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Table 20-5. McSPI Clocks
McSPI Clock
Associated PRCM Clock
Enable Bit
Autoidle Bit
Output
SPIm_FCLK
CORE_48M_FCLK
PRCM.CM_FCLKEN1_CORE.EN_MC
N/A
SPIm (with m=[1,4])
SPIm_ICLK
CORE_L4_ICLK
PRCM.CM_ICLKEN1_CORE.EN_MCS
PRCM.CM_AUTOIDLE1_CORE.AUTO_M
PIm (with m=[1,4])
CSPIm (with m=[1,4])
NOTE:
•
The PRCM CORE_48M_FCLK output is gated at the PRCM level, assuming that all
modules sharing it are disabled in the corresponding register. Disabling the McSPI
module is a necessary but insufficient condition.
•
The PRCM CORE_L4_ICLK output is gated at the PRCM level, assuming that all
modules sharing it are disabled in the corresponding register. Disabling the McSPI
module is a necessary but insufficient condition.
•
The PRCM.CM_AUTOIDLE1_CORE bit is used to link/unlink the McSPI module from
CORE_L4_ICLK-related clock domain transitions.
For more information about source clocks gating and domain transitions, see
, Power, Reset,
and Clock Management. For more information on power saving management, see
20.4.2.2 Power Domain
The McSPI modules belong to the CORE power domain (see
Table 20-6. Power Domain
Peripherals
Power Domain
McSPI modules
CORE power domain
20.4.2.3 Hardware Reset
As part of the CORE power domain, CORE_RST is issued by the PRCM module (for more information
about the CORE power domain implementation and CORE_RST signal, see
, Power, Reset,
and Clock Management). The module is reset by hardware when an active-low reset signal is asserted.
The hardware reset signal has a global reset effect on the module. All configuration registers and all
state-machines are reset in all clock domains (see
).
Table 20-7. McSPI Hardware Reset
Peripherals
Name
Comments
McSPI module
CORE_RST
Same as global reset
20.4.2.4 Software Reset
The SPIm.
[1] SOFTRESET bit controls the software reset of the SPI interface.
Writing 1 to this bit enables active software reset functionality, which is equivalent to a hardware reset.
The bit is automatically reset by hardware.
NOTE:
The SPIm.
register is not sensitive to software reset.
2988
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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