Texas Instruments OMAP36 Series, Техническое справочное руководство

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I2C _WAKE i
I2C .I2C_SYSC[2] ENAWAKEUP i
I2C .I2C_WE[0] AL_WE i
I2C .I2C_WE[1] NACK_WE i
I2C .I2C_WE[2] ARDY_WE i
I2C .I2C_WE[3] DRDY_WE i
I2C .I2C_WE[5] GC_WE
i
I2C .I2C_SYSC[9] CLKACTIVITY i
I2C .I2C_WE[6] STC_WE i
I2C .I2C_WE[8] BF_WE i
I2C .I2C_WE[9] AAS_WE i
I2C .I2C_WE[1 ] i 0 XUDF_WE
I2C .I2C_WE[1 ] i 1 ROVR_WE
AL event: arbitration lost detected
DRDY event: TX FIFO needs data (transmitter mode) or RX
FIFO must be read (receiver mode)
NACK event: non-ACK received from the slave device
ARDY event: registers are ready for access.
GC event: a general call has been received.
STC event: start condition detected asynchronously
BF event: the bus is free.
AAS event: the I C controller is addressed as a slave.
2
i2c-020
I2C .I2C_WE[13] RDR_WE i
I2C .I2C_WE[14] XDR_WE i
XDR event: the TX FIFO level is below the threshold
specified by the I2C .I2C_BUF[5:0] TXTRSH bit field, and the
i
amount of data left to be transferred is less than the value of
this threshold
RDR event: the RX FIFO threshold, specified by the
I2C .12C_BUF[13:8] RXTRSH bit field, is not reached after a
i
stop condition and the RX FIFO is not empty.
XUDF event: the I C controller has generated a transmission
underflow while transmitting.
2
ROVR event: the I C controller has generated an overrun
while receiving.
2
.
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HS I
2
C Integration
The wake-up request is composed of the merge of all wake-up events. Each wake-up event can be
separately enabled or disabled by setting the corresponding bit in the I2Ci.
I2C_WE register.
The global wake-up capability of the module can be enabled or disabled by setting the I2Ci. I2C_SYSC [2]
ENAWAKEUP bit (1: enabled; 0: disabled).
Figure 17-20 shows the wake-up generation flow.
Figure 17-20. HS I
2
C Wake-up Generation Flow
Table 17-6 lists all wake-up events with the corresponding enable/disable bit in the I2Ci. I2C_WE register.
Table 17-6. HS I
2
C Wake-Up Events
Wake-Up Supported Enable/Disable Bit
(1)
Event Generated When:
Event Name Configuration
Mode
AL event I
2
C mode only I2Ci. I2C_WE [0] AL_WE I2Ci in the device loses the arbitration of the I
2
C bus in master
transmitter mode.
NACK event I
2
C mode only I2Ci. I2C_WE [1] NACK_WE A nonacknowledgment has been generated on the I
2
C bus,
indicating a transmission error.
ARDY event I
2
C receive mode I2Ci. I2C_WE [2] ARDY_WE The current transaction is finished and the module registers
and SCCB read can be accessed.
mode
DRDY event I
2
C and SCCB I2Ci. I2C_WE [3] DRDY_WE The TX FIFO needs some data to be transferred or the RX
modes FIFO must be read.
(1)
To enable the corresponding wake-up event generation, set the bit to 1. To disable the corresponding wake-up event generation,
set the bit to 0.
2785 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated