Texas Instruments OMAP36 Series, Техническое справочное руководство

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High-Speed USB OTG Controller
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• DMA mode (transfer one or more packets)
• Interrupt enable
• Endpoint number
• L3 interconnect memory address (32 bits)
• Byte count
The DMA controller can issue single accesses (8-, 16-, or 32-bit) and also bursts (4 x 32-bit, 8 x 32-bit, or
16 x 32-bit) on the L3 interconnect. The start address provided to the DMA controller must be 32-bit
aligned.
22.1.4.5 Automatic Packet Splitting/Combining for Bulk Transfers
The high-speed USB controller offers the facility for bulk endpoints to store larger amounts of data in their
FIFOs than can be transferred in a single USB operation. In other words, the module includes a
configuration option that, if selected, allows larger data packets to be written to bulk TX endpoints, which
are then split into packets of an appropriate size for transfer across the USB. A similar option exists for
bulk RX endpoints, which, if selected, causes the module to combine the packet received across the USB
into larger data packets before being read by the application software.
The firmware can enable these options by setting the corresponding bits (MPRXE and MPTXE) in the
CONFIGDATA register. The necessary packet size information contains the payload size for one
transaction and a multiplier defining the maximum number of USB packets. The payload is required to be
either 8, 16, 32, 64, or (in case of high-speed transfers) 512 bytes; the multiplier can be any value up to
32.
22.1.4.6 High-Bandwidth Isochronous Endpoints
In the high-speed mode, isochronous endpoints can transfer up to three USB packets in any microframe
with a payload of up to 1024 bytes in each packet, corresponding to a data transfer rate of up to 3072
bytes per microframe (see Universal Serial Bus Specification Revision 2.0).
For TX endpoints, the high-speed USB controller supports this by allowing loading data packets of up to
3072 bytes (that is, 3 x 1024 bytes) into the associated endpoint FIFO, which is then automatically split
into USB packets of the maximum payload, or smaller to be transmitted in one microframe.
For RX endpoints, the module automatically combines all the USB packets received during a microframe
into a single packet of up to 3072 bytes (that is, 3 x 1024 bytes) within the RX FIFO.
The number of USB packets transferred per microframe and the maximum payload in each packet is
defined through the appropriate registers (RXMAXP and TXMAXP).
22.1.5 High-Speed USB OTG Controller Basic Programming Model
This section describes only the TI-specific programming model details.
22.1.5.1 High-Speed USB Controller Interface Selection
The TI High-Speed USB controller supports only the 12-pin/8-bit data version ULPI interface (see
Table 22-16 ).
The 8-pin, 4-bit version ULPI interface and 8-bit UTMI+ Level 3 interface are not supported.
The 12-pin/8-bit data SDR ULPI interface is selected through the USBOTG. OTG_INTERFSEL [1:0]
PHYSEL field set to 0x1.
22.1.5.2 Enable Simulation Acceleration Features
The USBOTG. OTG_SIMENABLE register is dedicated solely for simulation (see Table 22-18 ) and is used
to reduce timer length and, hence, the time taken for the test bench to run.
This special mode can be active only during simulation and must be disabled for normal operation. The
firmware must keep TM1 inactive (reset value) during normal operation. An accidental write to this register
can cause a malfunction.
3226 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated