camisp-091
lines
pixels
Dense
accesses
No accesses
Expand processing time per line,
leading to less dense access
pattern –
other requestors have
better latency
Preview engine, resizer, and
H3A always correspond to
L3/2
regardless of PCLK
CCDC and peak bandwidth
corresponds to PCLK clock
Public Version
www.ti.com
Camera ISP Basic Programming Model
Table 6-78. Camera ISP Central-Resource SBL Read-Buffer Underflow Events (continued)
Read port
Description
Resizer image from memory
No error can occur on this port because the resizer module
stops processing when no image data is ready.
Histogram image from memory
No error can occur on this port because the histogram module
stops processing when no image data is ready.
CSI1/CCP2B image from memory
No error can occur on this port because the CSI1/CCP2B
module stops processing when no image data is ready.
6.5.11.4 Camera ISP Central-Resource SBL Register Accessibility During Frame Processing
The central resource SBL registers are all busy-writable registers.
•
Busy-writable registers
–
These registers/fields can be read or written even if the module is busy. Changes to the underlying
settings occur instantaneously.
6.5.11.5 Camera ISP Central-Resource SBL Camera ISP Bandwidth Adjustments
For memory-to-memory operation, the camera ISP processes data at the highest possible data rate. If this
processing returns results long before real-time deadlines, the performance of other peripherals in the
system may be negatively affected. The camera ISP offers two kinds of adjustments that can slow down
data processing in this situation. One can be made when the sensor input to the CCDC is the input
source, and the other can be made when the memory is the source of the input image.
6.5.11.5.1 Camera ISP Central-Resource SBL Input From CCDC Video-Port Interface
The video-port interface delivers data at a rate independent of the pixel clock when the data reformatter is
enabled. By default, this rate is set to 100 MHz, which is fast enough to support a parallel interface clock
of 90 MHz or a CSI/CCP2B /CSI2 clock of 100 MHz. When the pixel clock is at a lower frequency, it is
unnecessary for the video-port interface to operate at such a high frequency. The
[21:16]
VPIF_FRQ field of the CCDC can be programmed to reduce the rate at which the video port delivers new
data to the other modules (Preview, H3A, and histogram). In effect, this register indirectly controls the
output bandwidth of the preview engine, resizer, and H3A. Depending on the input sensor clock, Users
can set this field appropriately and balance the bandwidth requirements to memory.
demonstrates how this register can expand processing time per line for lower PCLK frequencies.
Figure 6-120. Camera ISP Central-Resource SBL Video-Port Interface Bandwidth Balancing
1297
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...