Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Integration
5.2.1 Clocking, Reset, and Power-Management Scheme
5.2.1.1 Clocks
5.2.1.1.1 IVA2.2 Clocks
The IVA2.2 subsystem receives one single clock signal (IVA_CLK) from the PRCM.
NOTE: When the IVA2.2 subsystem does not require an internal clock, the internal clocks can be
disabled at the PRCM level by setting the PRCM.CM_FCLKEN_IVA2 EN_IVA2 bit to 0.
From this clock (IVA_CLK), three internal clocks are generated by the IVA2.2 system control module
(SYSC):
• CD0_CLK: Fastest IVA2.2 subsystem functional clock, dedicated to the DSP. Its frequency can be
adjusted at the PRCM level by setting the PRCM.CM_CLKSEL1_PLL_IVA2 and
PRCM.CM_CLKSEL2_PLL_IVA2 registers.
• CD1_CLK: Divide-by-two of the CD0_CLK clock
• CD2_CLK: Divide-by-two of the CD0_CLK clock
Generation of these three clocks is handled internally to the IVA2.2 subsystem by the SYSC module under
direct control of the PRCM.
Table 5-1 lists the clock domains in the IVA2.2 subsystem and shows the roles of the clocks.
Table 5-1. IVA2.2 Internal Clock
CD0 CD0_CLK DSP core + PMC + DMC
CD1 CD1_CLK UMC + power-down + interrupt controller
CD2 CD2_CLK EMC + IDMA + DSP megamodule external inte local interc
EDMA + MMU + SYSC + iVLCD + iME + iLF
NOTE: The internal clocks can be shut down by the PRCM module after the handshake protocol is
complete. To configure the PRCM so that internal clocks are hardware-supervised, set the
PRCM.CM_AUTOIDLE_PLL_IVA2[2:0] AUTO_IVA2_DPLL field to 0x1. For more
information, see
Chapter 3 , Power, Reset, and Clock Management.
The video sequencer module receives SEQ_CLK from CD2_CLK. This divided clock is generated in the
video accelerator/sequencer system configuration. For more information about the divided clock of the
sequencer, see
Section 5.4.10.1 , Clock Management.
CAUTION
Clock configurations depend on core voltage, and maximum clock frequencies
may not apply to production.
5.2.1.2 Resets
5.2.1.2.1 Hardware Resets
Figure 5-3 shows the seven hardware input reset signals at the boundary of the IVA2.2 subsystem:
• IVA2_RST1, connected to the DSP megamodule and EDMA modules
• IVA2_RST2, connected to the SYSC, MMU, improved variable-length coder/decoder (iVLCD), iME,
iLF, and local interconnect
• IVA2_RST3, connected to the sequencer
• CORE_RST, connected to the IVA2.2 subsystem wake-up generator (WUGEN) module
• RET_RST, connected to the subsystem WUGEN retention logic to reset registers that keep their value
697 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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