Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
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Table 5-92. Register Call Summary for Register L2CFG
IVA2.2 Subsystem Basic Programming Model
• IVA2.2 Boot Configuration : [0] [1] [2] [3] [4]
• Cache-Size Configuration : [5] [6] [7] [8]
• Cache Mode Configuration : [9] [10]
• External Memory : [11]
• Powering Down L2$ Memory While IVA2 is Active : [12] [13] [14] [15]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [16]
Table 5-93. L1PCFG
Address Offset 0x0000 0020
Physical address 0x0184 0020 Instance IVA2.2 GEMXMC
Description
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved L1PMODE
Bits Field Name Description Type Reset
31:3 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00000000
2:0 L1PMODE L1P Configuration Register RW 0x0
0x0: 0KB of L1P Cache
0x1: 4KB of L1P Cache
0x2: 8KB of L1P Cache
0x3: 16KB of L1P Cache
0x4: Maximum cache (32KB of L1P Cache)
Table 5-94. Register Call Summary for Register L1PCFG
IVA2.2 Subsystem Basic Programming Model
• IVA2.2 Boot Configuration : [0] [1] [2] [3]
• Cache-Size Configuration : [4] [5] [6] [7] [8]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [9]
Table 5-95. L1PCC
Address Offset 0x0000 0024
Physical address 0x0184 0024 Instance IVA2.2 GEMXMC
Description L1P Configuration Register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved POPER Reserved OPER
Bits Field Name Description Type Reset
31:19 Reserved Write 0s for future compatibility. Read returns 0. R 0x0000
18:16 POPER Previous value of the OPER field R 0x0
Read 0x0: L1P cache operates normally
Read 0x1: L1P Cache is frozen
15:3 Reserved Write 0s for future compatibility. Read returns 0. RW 0x0000
830 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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