Texas Instruments OMAP36 Series, Техническое справочное руководство

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Internal
CLKR
DR B7
B6
Data setup
Data hold
mcbsp-054
Public Version
McBSP Basic Programming Model
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Receive frame-synchronization pulses can be generated internally by the SRG or driven by an external
source. The source of frame synchronization is selected by programming the
McBSPi.
MCBSPLP_PCR_REG [10] FSRM bit. FSR is also affected by the
McBSPi. MCBSPLP_SRGR2_REG [15] GSYNC bit. For information about the effects of FSRM and
GSYNC, see Section 21.5.1.5.2.3.1 , Set the Receive Frame-Sync Mode.
When FSR and FSX are inputs (FSXM = FSRM = 0, external frame-synchronization pulses), the McBSP
module detects them on the internal falling edge of clock, internal CLKR, and internal CLKX, respectively.
The receive data arriving at the mcbspi_dr pin is also sampled on the falling edge of internal CLKR. These
internal clock signals are either derived from an external source via CLK(R/X) pins or driven by the SRG
clock (CLKG) internal to the McBSP module.
When FSR and FSX are outputs, implying that they are driven by the SRG, they are generated (transition
to their active state) on the rising edge of the internal clock, CLK(R/X). Similarly, data on the mcbsp_dx
pin is output on the rising edge of internal CLKX.
FSRP, FSXP, CLKRP, and CLKXP bit fields in the pin control register (McBSPi. MCBSPLP_PCR_REG )
configure the polarities of the FSR, FSX, CLKR, and CLKX signals, respectively. All frame-synchronization
signals (internal FSR, internal FSX) that are internal to the serial port are active high. If the serial port is
configured for external frame synchronization (FSR/FSX are inputs to McBSP), and FSRP = FSXP = 1,
the external active-low frame-synchronization signals are inverted before being sent to the receiver
(internal FSR) and transmitter (internal FSX). Similarly, if internal synchronization (FSR/FSX are output
pins and GSYNC = 0) is selected, the internal active-high frame-synchronization signals are inverted, if the
polarity bit FS(R/X)P = 1, before being sent to the FS(R/X) pin.
Figure 21-64 shows how data clocked by an external serial device using a rising edge can be sampled by
the McBSP receiver on the falling edge of the same clock.
Figure 21-64. Data Externally Clocked on a Rising Edge and Sampled on a Falling Edge
21.5.1.5.2.3.3 Set the SRG Frame-Sync Period and Pulse Width
The SRG can produce a clock signal, CLKG, and FSG. If the SRG is supplying receive or transmit frame
synchronization, you must program the bit fields FPER and FWID.
McBSPi. MCBSPLP_SRGR2_REG [11:0] FPER bit field is used to set the SRG frame-sync period and
McBSPi. MCBSPLP_SRGR1_REG [15:8] FWID bit field is used to set the SRG pulse width.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is
(FPER+1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG
cycles, which allows up to 4096 data bits per frame. When GSYNC=1, FPER is a don’t care value.
Each pulse on FSG has a width of (FWID+1) CLKG cycles. The eight bits of FWID allow a pulse width of 1
to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the programmed
word length.
The values in FPER and FWID are loaded into separate down–counters. The 12–bit FPER counter counts
down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8–bit FWID
counter counts down from the programmed value (255 maximum) to 0.
Figure 21-65 shows a frame-synchronization period of 16 CLKG periods (FPER=15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID=1).
3140 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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