DSI_IRQST
A
TUS
DSI_IRQ
DSI_VC3_IRQST
A
TUS
ECC_NO_CORRECTION_IRQ_EN
ECC_NO_CORRECTION_IRQ
CS_IRQ_EN
CS_IRQ
DSI_COMPLEXIO_IRQST
A
TUS
ULPSACTIVENOT_ALL1_IRQ_EN
ULPSACTIVENOT_ALL1_IRQ
ERRSYNCESC1_IRQ_EN
ERRSYNCESC1_IRQ
VIRTUAL_CHANNEL3_IRQ
PLL_RECAL_IRQ_EN
DSI complex I/O
DSI virtual channel 3
DSI protocol engine
.......
.......
31
0
0
6
DSI_VC0_IRQST
A
TUS
ECC_NO_CORRECTION_IRQ_EN
ECC_NO_CORRECTION_IRQ
CS_IRQ_EN
CS_IRQ
DSI virtual channel 0
.......
0
6
PLL_RECAL_IRQ
WAKEUP_IRQ_EN
WAKEUP_IRQ
HS_TX_TO_IRQ_EN
HS_TX_TO_IRQ
TA_TO_IRQ_EN
TA_TO_IRQ
COMPLEXIO_ERR_IRQ
VIRTUAL_CHANNEL0_IRQ
.......
.......
dss-160
Public Version
www.ti.com
Display Subsystem Integration
7.3.2.1.2 DSI Protocol Engine DMA Request
The DSI DMA requests are used to allow automatic transfer by the sDMA or MPU (with less efficiency and
through-put capability) from the DSI RX FIFO to the system memory and from the system memory to the
DSI TX FIFO. Two independent DMA requests for RX FIFO and TX FIFO for the same VC are supported.
7.3.2.1.3 RFBI DMA Request
The RFBI_DMA_REQ is used to receive data into the RFBI FIFO. The DMA request is always generated
when there is enough room in the FIFO to accept the full burst.
7.3.2.2
Interrupt Requests
The DSI protocol engine, the DSI complex I/O (DSI_IRQ), and the display controller (DISPC_IRQ)
generate one interrupt request each. The DSI_IRQ and DISPC_IRQ lines are merged together in a single
interrupt line.
One interrupt line (DSS_IRQ) is connected to two interrupt controllers:
•
MPU interrupt controller (M_IRQ_25 input line)
•
IVA interrupt handler (IVA2_IRQ[13] input line)
shows the interrupt tree for the DSI protocol engine and DSI complex I/O in detail.
Figure 7-65. DSI Interrupt Tree
1629
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...