Texas Instruments OMAP36 Series, Техническое справочное руководство

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McBSP Register Manual
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Bits Field Name Description Type Reset
31:16 RESERVED Read returns 0x0. R 0x0000
15 GSYNC Sample Rate Generator Synchronization RW 0x0
Only used when the external clock (CLKS) drives the
SRG clock (CLKSM=0)
0x0: The SRG clock (CLKG) is free running.
0x1: The SRG clock (CLKG) is running.
But CLKG is resynchronized and frame-sync signal
(FSG) is generated only after detecting the receive
frame-synchronization signal (FSR). Also, frame period,
FPER, is a don't care because the period is dictated by
the external frame-sync pulse.
14 CLKSP CLKS Polarity Clock Edge Select RW 0x0
Only used when the external clock CLKS drives the SRG
clock (CLKSM=0).
0x0: Rising edge of CLKG and FSG.
0x1: Falling edge of CLKG and FSG.
13 CLKSM McBSP SRG Clock Mode RW 0x1
0x0:
SCLKME=0: SRG clock derived from the CLKS pin.
SCLKME=1: SRG clock derived from the CLKR input pin.
0x1:
SCLKME=0: SRG clock derived from the McBSPi_ICLK
clock.
SCLKME=1: SRG clock derived from the CLKX input pin.
12 FSGM Sample Rate Generator Transmit Frame-Synchronization RW 0x0
Mode
Used when FSXM=1 in the PCR.
0x0: Transmit frame-sync signal (FSX) is generated when
transmit buffer is not empty.
When FSGM=0, FPER and FWID are used to determine
the frame synchronization period and width (external FSX
is gated by the buffer empty condition).
0x1: Transmit frame-sync signal driven by the SRG
frame-sync signal, FSG.
11:0 FPER Frame Period. This value + 1 determines when the next RW 0x000
frame-sync signal becomes active.
Range: 1 to 4096 CLKG periods
Table 21-61. Register Call Summary for Register MCBSPLP_SRGR2_REG
McBSP Integration
• Clocks : [0] [1] [2] [3] [4]
McBSP Functional Description
• Clocking and Framing Data : [5] [6]
• McBSP SRG : [7] [8] [9] [10]
• Frame Sync Generation in the SRG : [11] [12] [13] [14] [15] [16] [17]
• Synchronizing SRG Outputs to an External Clock : [18] [19] [20] [21] [22] [23] [24] [25] [26]
• Underflow in the Transmitter : [27] [28] [29]
McBSP Basic Programming Model
• McBSP Initialization Procedure : [30]
• Reset and Initialization Procedure for the Sample Rate Generator : [31]
• Receiver Configuration : [32] [33] [34] [35] [36] [37]
• Transmitter Configuration : [38] [39]
McBSP Register Manual
• McBSP Register Mapping Summary : [40] [41] [42] [43] [44]
3170Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated