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NOTE: When the McBSP4 module does not require the interface clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP4 bit (PRCM.CM_ICLKEN_PER[2]) in
the PRCM registers. The clock is effectively cut, provided the other modules that receive it
do not require it. For more information, see
Chapter 3 , Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off PER_L4_ICLK clock are met the PRCM
automatically launches a hardware handshake protocol to ensure McBSP4 is ready to have
this clock switched off. Namely, the PRCM asserts an idle request to McBSP4. For more
details, see
Chapter 3 , Power Reset and Clock Management.
It is also possible to activate an autoidle mode for this clock (PRCM.CM_AUTOIDLE_PER[2]
register AUTO_MCBSP4 bit set to 1). In this case, McBSP4_ICLK follows the PER_L4 clock
domain behavior on the device. For more information, see
Chapter 3 , Power Reset and
Clock Management.
21.3.2.2.5 McBSP5 Clocks
The McBSP5 module is clocked by a functional clock (CLKS or CLKX) and an interface clock
(McBSP5_ICLK).
• The functional clock is used to generate control signals depending on the module internal configuration
(see
Section 21.4 ). For McBSP5 module, the functional clock comes from the CLKS signal, the CLKX
signal, or the CLKR signal. The choice between these three clocks is defined by the SCLKME bit of the
MCBSP5.
MCBSPLP_PCR_REG [7] register and the CLKSM bit of the
MCBSP5. MCBSPLP_SRGR2_REG [13] register.
The CLKS signal of the McBSP5 module is linked to an internal clock (CORE_96M_FCLK) provided by
PRCM. The CLKS signal can also be linked to an external signal through the mcbsp_clks pin of the
device boundary. The MCBSP5_CLKS bit of the CONTROL.CONTROL_DEVCONF1[4] register is
used to select the McBSP5 module CLKS signal source:
– 0: The CLKS source is from the CORE_96M_FCLK.
– 1: The CLKS source is from the mcbsp_clks pin.
For more information, see Chapter 13 , System Control Module.
NOTE: When the McBSP5 module does not require the functional clock anymore, the software can
disable it at the PRCM level by setting the EN_MCBSP5 bit
(PRCM.CM_FCLKEN1_CORE[10]) in the PRCM registers. The clock is effectively cut,
provided the other modules that receive it do not require it. For more details, see
Chapter 3 ,
Power Reset and Clock Management.
At PRCM level, when all the conditions to shut-off CORE_96M_FCLK clock are met the
PRCM automatically launches a hardware handshake protocol to ensure McBSP5 is ready to
have this clock switched off. Namely, the PRCM asserts an idle request to McBSP5. For
more details, see
Chapter 3 , Power Reset and Clock Management.
Only, the CLKX signal is connected by mcbsp5_clkx pads. The CLKR signal is connected to the CLKX
signal. These signals are used like functional clocks by the intermediary of SRG.
• The McBSP5_ICLK runs at the L4 core interconnect clock speed. It is used to trigger access to the
McBSP5 L4 interface and McBSP5 configuration interface via the MPU/IVA2.2 shared bus. It can also
be an input clock for the McBSP sample-rate generator (clock divider), depending on the module
configuration (see
Section 21.4.3 ). Its source is either the CORE_L4_ICLK signal.
3078 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated