Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Register Manual
Bits Field Name Description Type Reset
24 RSZ_DONE_IRQ RESIZER module - resizer processing done event. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
23:22 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0x0
Clr
21 CBUFF_IRQ A circular buffer event is pending. Check submodule's interrupt R/W/1to 0
status register. Clr
READS:
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
20 PRV_DONE_IRQ PREVIEW module - processing done event. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
19 CCDC_LSC_PREFETCH_ERRO The prefetch error indicates when the gain table was read to slowly R/W/1to 0
R from SDRAM. Clr
READS:
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
18 CCDC_LSC_PREFETCH_COMP Indicates current state of the prefetch buffer. R/W/1to 0
LETED READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
17 CCDC_LSC_DONE The event is triggered when the internal state of LSC toggles from R/W/1to 0
BUSY to IDLE. Clr
READS:
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
16 HIST_DONE_IRQ HIST module - processing done event. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
15:14 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
13 H3A_AWB_DONE_IRQ H3A module - auto exposure and auto white balance processing R/W/1to 0
done event. Clr
READS:
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
1309 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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