Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Register Manual
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Table 3-137. CORE_CM Register Summary (continued)
Register Name Type Register Width Address Offset Physical Address Reset Type
(Bits)
CM_FCLKEN3_CORE RW 32 0x0000 0008 0x4800 4A08 W
CM_ICLKEN1_CORE RW 32 0x0000 0010 0x4800 4A10 W
Reserved for non-GP devices. RW 32 0x0000 0014 0x4800 4A14 W
CM_ICLKEN3_CORE RW 32 0x0000 0018 0x4800 4A18 W
CM_IDLEST1_CORE R 32 0x0000 0020 0x4800 4A20 C
Reserved for non-GP devices. R 32 0x0000 0024 0x4800 4A24 C
CM_IDLEST3_CORE R 32 0x0000 0028 0x4800 4A28 C
CM_AUTOIDLE1_CORE RW 32 0x0000 0030 0x4800 4A30 W
Reserved for non-GP devices. RW 32 0x0000 0034 0x4800 4A34 W
CM_AUTOIDLE3_CORE RW 32 0x0000 0038 0x4800 4A38 W
CM_CLKSEL_CORE RW 32 0x0000 0040 0x4800 4A40 W
CM_CLKSTCTRL_CORE RW 32 0x0000 0048 0x4800 4A48 W
CM_CLKSTST_CORE R 32 0x0000 004C 0x4800 4A4C C
3.8.1.5.2 CORE_CM Registers
Table 3-138. CM_FCLKEN1_CORE
Address Offset 0x0000 0000
Physical Address 0x4800 4A00 Instance CORE_CM
Description Controls the module functional clock activity.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
EN_I2C3 EN_I2C2 EN_I2C1
EN_HDQ
EN_MMC3 EN_MMC2 EN_MMC1
EN_GPT11 EN_GPT10 EN_UART2 EN_UART1
RESERVED RESERVED RESERVED
EN_MCSPI4 EN_MCSPI3 EN_MCSPI2 EN_MCSPI1
EN_MCBSP5 EN_MCBSP1
Bits Field Name Description Type Reset
31 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
30 EN_MMC3 MMC3 functional clock control. RW 0x0
0x0: MMC3 functional clock is disabled
0x1: MMC3 functional clock is enabled
29:26 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
25 EN_MMC2 MMC2 functional clock control. RW 0x0
0x0: MMC2 functional clock is disabled
0x1: MMC2 functional clock is enabled
24 EN_MMC1 MMC1 functional clock control. RW 0x0
0x0: MMC 1 functional clock is disabled
0x1: MMC 1 functional clock is enabled
23 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
22 EN_HDQ HDQ-1 wire functional clock control. RW 0x0
0x0: HDQ functional clock is disabled
0x1: HDQ functional clock is enabled
474 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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