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PRCM Register Manual
Bits
Field Name
Description
Type
Reset
31:4
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0000000
3
OFFMODE_POL
Controls the polarity of the sys_offmode signal
RW
0x1
0x0: sys_offmode is active low
0x1: sys_offmode is active high
2
CLKOUT_POL
Controls the external output clock polarity when disabled
RW
0x0
0x0: sys_clkout is gated low when inactive
0x1: sys_clkout is gated high when inactive
1
CLKREQ_POL
Controls the polarity of the sys_clkreq signal
RW
0x1
0x0: sys_clkreq is active low
0x1: sys_clkreq is active high
0
EXTVOL_POL
Controls the polarity of sys_vmode signal
RW
0x0
0x0: sys_vmode signal is active low
0x1: sys_vmode signal is active high
Table 3-476. Register Call Summary for Register PRM_POLCTRL
PRCM Functional Description
•
Clock Request (sys_clkreq) Control
:
•
System Clock Oscillator Control
•
External Output Clock1 (sys_clkout1) Control
•
•
Direct Control With VMODE Signals
:
PRCM Use Cases and Tips
•
:
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
Table 3-477. PRM_VOLTSETUP2
Address Offset
0x0000 00A0
Physical Address
0x4830 72A0
Instance
Global_Reg_PRM
Description
This register allows setting the overall setup time of VDD1 and VDD2 regulators. This register is used
when exiting OFF mode and when the Power IC manages the sequencing of the voltages regulation
steps.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
OFFMODESETUPTIME
Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x0000
15:0
OFFMODESETUPTIME
Number of 32kHz clock cycles for the overall setup time
RW
0x0000
of VDD1 and VDD2 regulators.
Table 3-478. Register Call Summary for Register PRM_VOLTSETUP2
PRCM Basic Programming Model
•
PRM_VOLTSETUP (Voltage Setup Time Register)
•
PRM_VOLTOFFSET (Voltage Offset Register)
PRCM Register Manual
•
Global_Reg_PRM Register Summary
:
641
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...