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PRCM Basic Programming Model
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To configure the parameters of the voltage processor module, both the SmartReflex and the voltage
processor modules are disabled. This ensures that no voltage command is passed to the SMPS while
the OPP change is being configured.
PRCM.PRM_VPn_CONFIG[0] VPENABLE 0x0 Disable the voltage processor module.
SRn. SRCONFIG [11] SR_EN 0x0 Disable the SmartReflex module.
2. Force SMPS voltage update.
The voltage processor INITVDD bit is set so that the initial voltage in the voltage processor module is
set according to the target OPP (OPPy). Before asserting the force update command, the voltage
processor must be in idle mode. The SMPS is force-updated to switch from OPPx to OPPy by
asserting the FORCEUPDATE bit of the voltage processor.
NOTE: The SmartReflex and voltage processor interrupts are masked.
PRCM.PRM_VPn_CONFIG[0] INITVOLTAGE Configured according to the target OPP voltage value.
PRCM.PRM_VPn_CONFIG[15:8] INITVDD 0x1 Triggers a write of the value in the INITVOLTAGE bit
field in the voltage processor
PRCM. PRM_VPn_CONFIG[1] FORCEUPDATE 0x1 Force update of the SMPS.
NOTE: To support OPP50, the DPLL2 and DPLL1 bypass clocks must be set properly. The DPLL1
bypass clock must always be set to CORE_CLK/2. The DPLL2 bypass clock must always be
set to CORE_CLK/2. For more information, see
Section 3.5.3.8.2 , Interface and Peripheral
Functional Clock Configurations
3.6.6.9 Event Generator Programming Examples
The event generator feature allows the MPU power domain to be switched between on and off (or placed
in idled mode). This is intended to implement an efficient activity modulation of the MPU power state with
minimum software support.
When the event generator is activated, the PRCM module ensures that the CORE power domain always
follows the MPU power domain activity.
The PRCM. PM_EVGENONTIM_MPU and PRCM. PM_EVGENOFFTIM_MPU registers of the event
generator counter allow the configuration of the on and off durations (the number of system clock cycles)
for the MPU power domain. The PRCM.
PM_EVGENCTRL_MPU register allows the enabling/disabling of
the event generator feature and control of the way on and off values are loaded in the counter.
There are three ways to load the counter with the next counting value:
• Load on update of the corresponding PRCM. PM_EVGENONTIM_MPU or
PRCM. PM_EVGENOFFTIM_MPU register.
• Load the on-time value when the MPU power domain wakes up, and the off-time value when the MPU
power domain starts the sleep transition (the MPU executes the WFI instruction).
• Automatically load the on-time value when the off-time value expires, and automatically load the
off-time value when the on-time value expires.
When the counter times out at the end of the on/off time, it triggers the interrupt/wake-up transition,
respectively. The software can use the on-time interrupt to trigger the WFI processor instruction to idle the
processor clock. Similarly, the wake-up event at the end of the off time restarts the processor clock and
interrupts the processor. To enable the corresponding interrupts, the MPU interrupts mask must be set in
the PRCM.
PRM_IRQENABLE_MPU register.
446 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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