Public Version
IVA2.2 Subsystem Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
31:13
RESERVED
Write 0s for future compatibility
RW
0x0
Read returns 0
12:0
BUFPTR
Set a pointer inside Ring Buffer from which bitstream will be written.
RW
0x0000
After the completion, the final pointer is shown. Must be even
number.
If IBUF0 is selected in
, bit 12 select if IBUF0_A
(0) or IBUF0_B (1) is used.
Table 5-647. Register Call Summary for Register CAVLC_BUFPTR
IVA2.2 Subsystem Basic Programming Model
•
Setting Up Registers for CAVLC Operation
IVA2.2 Subsystem Register Manual
•
iVLCD Register Mapping Summary
Table 5-648. CAVLC_BITPTR
Address Offset
0x0000 1154
Physical Address
0x0008 1154
Instance
iVLCD
Description
This register sets the number of valid MSBs in stream word registers.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
BITPTR
Bits
Field Name
Description
Type
Reset
31:5
RESERVED
Write 0s for future compatibility
RW
0x000
Read returns 0
4:0
BITPTR
Set the number of valid MSBs in stream word registers. The
RW
0x00
bitstream to be generated follows the valid bits. It shows the number
of valid MSBs in stream word registers after completion of the job.
Table 5-649. Register Call Summary for Register CAVLC_BITPTR
IVA2.2 Subsystem Basic Programming Model
•
Setting Up Registers for CAVLC Operation
IVA2.2 Subsystem Register Manual
•
iVLCD Register Mapping Summary
Table 5-650. CAVLC_STRMWDU
Address Offset
0x0000 1158
Physical Address
0x0008 1158
Instance
iVLCD
Description
Upper half of 32-bit Stream Word Register
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
STRMWDU
Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Write 0s for future compatibility
RW
0x0000
Read returns 0
15:0
STRMWDU
Upper half of 32-bit Stream Word Register. Write bits from MSB so
RW
0x0000
that bitstream to be generated follows them. After the completion of
the job, remaining bits, which is less than 32 and not written to
Image Buffer, is shown.
1038
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...