Public Version
PRCM Functional Description
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3.5.4.6.1 USBHOST SAR Sequences
3.5.4.6.1.1 Save Sequence on Sleep Transition
A precondition to the save sequence on sleep transition is that the save-and-restore mechanism is
enabled (the PRCM.
[4] SAVEANDRESTORE bit is set to 1). The sequence is
initiated when the power domain switches from ON to OFF power state.
1. The PRCM module activates USBHOST_SAR_FCLK and starts the save sequence.
2. When the USBHOST power domain is idled (all clocks of the power domain are gated), the PRM
initiates the power domain transition to OFF power state by setting the
PRCM.
[1:0] POWERSTATE bit field to 0x0.
3. When the save sequence completes, USBHOST_SAR_FCLK is gated.
4. The power domain sleep transition to OFF power state completes.
3.5.4.6.1.2 Restore Sequence on Wake-Up Transition
A precondition to the restore sequence on wake-up transition is that the save-and-restore mechanism is
enabled (the PRCM.
[4] SAVEANDRESTORE bit is set to 1). The sequence is
initiated when the power domain switches from off to on power state.
1. The PRCM switches the power domain to ON power state.
2. The PRCM asserts the USBHOST domain reset. The functional reset is released locally when the
functional clocks are back.
3. The PRCM releases the USBHOST domain reset.
4. The PRCM module activates USBHOST_SAR_FCLK and starts the restore sequence.
5. When the restore sequence completes, USBHOST_SAR_FCLK is gated.
6. The power domain wake-up transition to ON power state completes.
3.5.4.6.2 USB TLL SAR Sequences
3.5.4.6.2.1 Save Sequence on Sleep Transition
A precondition to the save sequence on sleep transition is that the save-and-restore mechanism is
enabled (the PRCM.
[4] SAVEANDRESTORE bit is set to 1). The sequence is
initiated when the power domain switches from ON to Open Switch Retention (OSWR) or OFF power
state.
1. When the CORE power domain is idled (all clocks of the power domain are gated), the PRM initiates
the power domain transition to OFF or OSWR power state by setting the
PRCM.
[1:0] POWERSTATE bit field to 0x0 or 0x1.
2. The PRCM module activates USBTTL_SAR_FCLK and starts the save sequence.
3. When the save sequence completes, USBTTL_SAR_FCLK is gated.
4. The power domain sleep transition to OFF or OSWR power state completes.
3.5.4.6.2.2 Restore Sequence on Wake-Up Transition
A precondition to the restore sequence on wake-up transition is that the save-and-restore mechanism is
enabled (the PRCM.
[4] SAVEANDRESTORE bit is set to 1). The sequence is
initiated when the power domain switches from OFF or OSWR to ON power state.
1. 1. PRCM switches the power domain to ON power state.
2. Assert CORE domain reset (must override the functional stall conditions of the reset manager). The
functional reset is released locally when the functional clocks are back.
3. Release CORE domain reset.
4. The PRCM module activates the USBTLL_SAR_FCLK and starts the restore sequence.
5. When the restore sequence completes, USBTLL_SAR_FCLK is gated.
6. The power domain wake-up transition to ON power state completes.
368
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
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Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...