Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 562 / 3738

Public Version
PRCM Register Manual
www.ti.com
Bits Field Name Description Type Reset
21 VP2_TRANXDONE_ST Voltage Processor 2 transaction completion status. This RW 0x0
status is set when a transaction is completed in the
voltage processor. It is cleared by software.
Read 0x0: Voltage Processor 2 transaction done event is
false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 transaction done event is
true (pending)
Write 0x1: Status bit is cleared to 0.
20 VP2_EQVALUE_ST Voltage Processor 2 voltage value change event. This RW 0x0
status is set when an update has been requested but the
new voltage value is the same as the current SMPS
voltage value. It is cleared by software.
Read 0x0: Voltage Processor 2 no voltage value change
event is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 no voltage value change
event is true (pending)
Write 0x1: Status bit is cleared to 0.
19 VP2_NOSMPSACK_ST Voltage Processor 2 timeout event status. This status is RW 0x0
set when the timeout occured before the SMPS
acknowledge. It is cleared by SW.
Read 0x0: Voltage Processor 2 timeout event is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 timeout event is true
(pending)
Write 0x1: Status bit is cleared to 0.
18 VP2_MAXVDD_ST Voltage Processor 2 voltage higher limit event status. RW 0x0
This status is set when the voltage higher limit is
reached. It is cleared by SW.
Read 0x0: Voltage Processor 2 voltage higher limit event
is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 voltage higher limit event
is true (pending)
Write 0x1: Status bit is cleared to 0.
17 VP2_MINVDD_ST Voltage Processor 2 voltage lower limit event status. This RW 0x0
status is set when the voltage lower limit is reached. It is
cleared by SW.
Read 0x0: Voltage Processor 2 voltage lower limit event
is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 voltage lower limit event
is true (pending)
Write 0x1: Status bit is cleared to 0.
16 VP2_OPPCHANGEDONE_ST Voltage Processor 2 OPP change done status. RW 0x0
Read 0x0: Voltage Processor 2 OPP change done event
is false
Write 0x0: Status bit unchanged
Read 0x1: Voltage Processor 2 OPP change done event
is true (pending)
Write 0x1: Status bit is cleared to 0.
562 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated