Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
Bits Field Name Description Type Reset
1 RESERVED Reserved RW 0x0
0 RESERVED Write 0s for future compatibility. Reads return zero. RW 0x0
Table 10-168. Register Call Summary for Register SDRC_DLLA_CTRL
SDRAM Controller (SDRC) Subsystem
• Power Management : [0]
• Power-Saving Features : [1] [2]
• DLL/CDL Configuration : [3] [4] [5] [6] [7] [8]
• Memory Power Management : [9] [10]
• SDRC Register Summary : [11]
Table 10-169. SDRC_DLLA_STATUS
Address Offset 0x0000 0064
Physical Address 0x6D00 0064 Instance SDRC
Description This register reflects the current status of the DLL A.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED RESERVED
LOCKSTATUS
Bits Field Name Description Type Reset
31:3 RESERVED Reads return zeros. R 0x00000000
2 LOCKSTATUS DLL lock status R 0x0
0x0: The DLL is not locked.
0x1: The DLL is locked.
1 RESERVED Reads return zero. R 0x0
0 RESERVED Reads return zero. R 0x0
Table 10-170. Register Call Summary for Register SDRC_DLLA_STATUS
SDRAM Controller (SDRC) Subsystem
• SDRC Register Summary : [0]
Table 10-171. SDRC_POWER_REG
Address Offset 0x0000 0070
Physical Address 0x6D00 0070 Instance SDRC
Description This SDRC power-management register defines the global power-management policy (shared by
CS0/CS1).
Type RW
2321 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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