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Camera ISP Functional Description
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– An end-of-line occurs. The DU (even if not full) is transferred to the memory, and a command is
issued.
6.4.9.2.3 Camera ISP Shared Buffer Logic Read Buffer Logic (RBL) and Read Buffer
The central resource SBL uses multiple RBL blocks to interface between the modules' read ports and the
read-buffer memory.
• One RBL is instantiated for each module read port.
• Each RBL is responsible for accepting input data from the read-buffer memory and for sending the
input data to the read port of the corresponding module.
• Each RBL is responsible for tracking all corresponding DUs in the read-buffer memory. There can be 2
or 4 DUs in the read buffer associated with a RBL.
• Unlike the WBL, the RBL is not responsible for issuing the commands to memory; each individual
module is responsible for doing this.
Two read ports are shared:
•
Between the PREVIEW module dark frame and the CCDC lens-shading compensation input
• Between the PREVIEW module and the CSI1/CCP2B module data read input
They can only be used by one module at a given time because there is no arbitration mechanism.
Software must enable only one of the two possible features attached to a port and to select the correct
multiplexer configuration using the
ISP_CTRL [27] SBL_SHARED_RPORTA and ISP_CTRL [28]
SBL_SHARED_RPORTB registers.
6.4.9.2.4 Camera ISP Shared Buffer Logic Arbitration
The central-resource SBL arbitrates between module requests, based on fixed priorities. Read and write
requests are arbitrated independently.
A total of 8 commands can be active at a time. When a new slot opens, the highest-priority transfer enters
the command queue.
RBLs/WBLs are ensured access to the read/write buffer memories at least once every other cycle.
NOTE: The hardware uses burst. All bursts are precise; the total number of transfers in the burst is
known at the start of the burst. All writes are posted.
6.4.9.3 Camera ISP Shared Buffer Logic Memories
The central-resource shared-buffer module has three memories:
• READ BUFFER: Shared by all modules 256 x 128 bits.
• WRITE BUFFER 0: Used only by the resizer module 256 x 128 bits.
• WRITE BUFFER 1: Shared by all modules except RESIZER 256 x 128 bits.
6.4.9.4 Camera ISP Shared Buffer Logic Debug Registers
Some registers are available for debugging data transfers between a module and external memory. The
read-only debug registers are divided into two categories:
• 8 global request registers to capture information about any of the 52 module request registers at a
given time. Each register provides information about one DU. The number 16 corresponds to the
maximum number of outstanding requests, according to the protocol. Each global request register
provides the following information:
– Individual module register command number. For modules with 2 individual requesters, this field
displays either 0 or 1. For modules with 4 individual requesters, this field displays 0, 1, 2, or 3.
– Source or destination module
– Data-flow direction
– Valid bit
• 52 individual module request registers (read or write information). Each register provides information
1232 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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