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Display Subsystem Basic Programming Model
The register DSS.
defines the allocated number of 33-bit values for each VC in
the RX FIFO and the start address for each VC. Only the enabled VCs should be taken into account. to
change the size of the space of the memory allocated for a specific VC, the VC should be disabled by
resetting the DSS.
[0] VC_EN bit to 0. The whole FIFO may not be used by the entire VC
at a given time since a VC can be disabled to change one or multiple parameters. Software users are
responsible for correctly configuring the start address and the size for each VC.
indicates the corresponding values for the size of the space allocated in the FIFO:
Table 7-66. Virtual Channel RX FIFO Size Values
.VCx_FIFO_SIZE[x = 0, 3]
Space Size (up to the size of the FIFO)
0
0 x 33 bits
1
32 x 33 bits
2
64 x 33 bits
3
96 x 33 bits
4
128 x 33 bits
The total size of RX FIFO is 128*33 bits. Therefore, the sum of all virtual channel FIFO allocation cannot
exceed 128*33 bits.
indicates the start address of the space in the FIFO.
Table 7-67. Virtual Channel RX FIFO Start Address
.VCx_FIFO_ADD[x = 0, 2]
Start Address
0
0
1
32
2
64
3
96
4
128
CAUTION
There must be no overlap of different VCs spaces.
While reading the received bytes in the RX FIFO, only the DSS.
register is used since the hardware does not keep track of the header position for long packets and
start/end of each packet. The software must extract the information from the bytes read from the RX FIFO.
There is no specific hardware to track the received bytes in the RX FIFO. The
DSS.
and DSS.
registers are
not used.
The ECC is only used by the first header when receiving multiple packets during the same LP RX transfer
from the peripheral since the DSI Protocol engine does not parse the header to identify the length of the
packets. In case of multiple packets, the Check-sum does not be enabled since the hardware checks the
check-sum considering a single packet. The ECC in the first header is used to correct and check the
header. For the following headers in the same LP RX transfer, the hardware does not detect any header
and cannot check or/and detect errors in the headers of the packets except for the first packet.
When the RX FIFO is empty:
•
there is no OCP error generated
•
the commands are accepted and the data for the responses are 0s
7.5.4.10.3 Command Mode DMA Requests
The DMA requests (DSI_DMA_REQ) are used to allow automatic transfer by the system DMA or MPU
(with less efficiency and through-put capability) from the DSI RX FIFO to the system memory and from the
1745
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
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