Public Version
PRCM Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
31:3
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
2
IVA2_DPLL_ST
DPLL2 recalibration event status
RW
0x0
Read 0x0: DPLL2 recalibration event is false
Write 0x0: Status bit unchanged
Read 0x1: DPLL2 recalibration event is true (pending)
Write 0x1: Status bit is cleared to 0.
1
FORCEWKUP_ST
Force wake-up IVA2 domain transition completed event
RW
0x0
status
Read 0x0: Wake-up event is false
Write 0x0: Status bit unchanged
Read 0x1: Wake-up event is true (pending)
Write 0x1: Status bit is cleared to 0.
0
WKUP_ST
IVA2 peripherals group wake-up event status
RW
0x0
Read 0x0: Wake-up event is false
Write 0x0: Status bit unchanged
Read 0x1: Wake-up event is true (pending)
Write 0x1: Status bit is cleared to 0.
Table 3-311. Register Call Summary for Register PRM_IRQSTATUS_IVA2
PRCM Functional Description
•
•
:
PRCM Basic Programming Model
•
Interrupt Configuration Registers
:
PRCM Register Manual
•
Table 3-312. PRM_IRQENABLE_IVA2
Address Offset
0x0000 00FC
Physical Address
0x4830 60FC
Instance
IVA2_PRM
Description
The interrupt enable register allows masking/unmasking the module internal sources of interrupt, on a
event-by-event basis. This registers applies on the interrupt line 0 mapped to the IVA2 Wake-Up
Generator.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
WKUP_EN
FORCEWKUP_EN
IVA2_DPLL_RECAL_EN
Bits
Field Name
Description
Type
Reset
31:3
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x00000000
2
IVA2_DPLL_RECAL_EN
DPLL2 recalibration mask
RW
0x0
0x0: DPLL2 recalibration event is masked
0x1: DPLL2 recalibration event generates an interrupt
558
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...