Public Version
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SGX Overview
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Industry-standard API support – Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG v1.0.1
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Fine-grained task switching, load balancing, and power management
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Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction
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Programmable high-quality image anti-aliasing
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POWERVR SGX core MMU for address translation from the core virtual address to the external
physical address (up to 4GB address range)
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Fully virtualized memory addressing for OS operation in a unified memory architecture
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Advanced and standard 2D operations [e.g., vector graphics, BLTs (block level transfers), ROPs
(raster operations)]
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32K stride support
8.1.2 SGX 3D Features
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Deferred pixel shading
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On-chip tile floating point depth buffer
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8-bit stencil with on-chip tile stencil buffer
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8 parallel depth/stencil tests per clock
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Scissor test
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Texture support:
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Cube map
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Projected textures
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2D textures
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Nonsquare textures
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Texture formats:
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RGBA 8888, 565, 1555
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Monochromatic 8, 16, 16f, 32f, 32int
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Dual channel, 8:8, 16:16, 16f:16f
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Compressed textures PVR-TC1, PVR-TC2, ETC1
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Programmable support for all YUV formats
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Resolution support:
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Frame buffer maximum size = 2048 x 2048
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Texture maximum size = 2048 x 2048
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Texture filtering:
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Bilinear, trilinear, anisotropic
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Independent minimum and maximum control
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Antialiasing:
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4x multisampling
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Up to 16x full scene anti-aliasing
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Programmable sample positions
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Indexed primitive list support
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Bus mastered
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Programmable vertex DMA
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Render to texture:
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Including twiddled formats
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Auto MipMap generation
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Multiple on-chip render targets (MRT).
Note: Performance is limited when the on-chip memory is not available.
8.1.3 Universal Scalable Shader Engine (USSE) – Key Features
The USSE is the engine core of the POWERVR SGX architecture and supports a broad range of
instructions.
1967
SWPU177N – December 2009 – Revised November 2010
2D/3D Graphics Accelerator
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...