Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
Requests sent to the SDRC are treated in order. The four transactions limit in the SDRC look-ahead FIFO
ensures that high-priority requests performance is not hampered by a succession of SDRAM page
close/page open cycles due to previous lower priority requests already accepted by the SDRC. With this
limit, requests not accepted by the SDRC will have to go through the SMS arbitration at a later time. If a
high-priority request has arrived in the SMS in the mean time, it will be passed to the SDRC before any
lower-priority request, as defined in the regular SMS arbitration scheme.
10.2.4.4.3 Address Multiplexing
A flexible address scheme allows for the support of any new type of SDRAM address multiplexing and
density.
The programming model has changed but is still compatible with the legacy fixed address scheme. Both
chips, hence both CS must use the same address scheme (fixed or flexible), but can use different address
multiplexing configurations.
A dedicated bit controls the address scheme used: the legacy fixed address scheme or the new flexible
address scheme:
• The legacy fixed address scheme is selected when the SDRC. SDRC_MCFG_p [19]
ADDRMUXLEGACY bit is set to 0 (where p = 0 or 1 for SDRC CS0 or CS1).
• A new flexible address-muxing scheme configuration is selected with the SDRC. SDRC_MCFG_p [19]
ADDRMUXLEGACY bit set to 1 (where p = 0 or 1 for SDRC CS0 or CS1).
To use this new flexible address scheme, configure the row address width and the column address with
the SDRC.
SDRC_MCFG_p [26:24] RASWIDTH and SDRC. SDRC_MCFG_p [22:20] CASWIDTH fields.
For more information about fixed address multiplexing configurations for SDRAM components, see
Section 10.2.2.2.3 , Address Multiplexing.
10.2.4.4.4 Bank Allocation Setting
10.2.4.4.4.1 System Address Decoding
The SDRC has a 64-bit slave interface connected to the L3 main system interconnect. The regular
allocation is to see the system address bus as the concatenation bank-row-column. The SDRC controller
translates the interconnect request (read or write to memory for instance) into a series of commands and
bank, row, column signals. The commands are sent to the external SDRAM through the sdrc_ncs,
sdrc_nras, sdrc_ncas and sdrc_nwe signals. The bank, row and column addresses are sent through
sdrc_a and sdrc_ba with the associated command. Those words can be defined as follow:
• Bank: the address of one of the four (or two) banks
• Row: the address of a page
• Column: the address of a word in a page
The bank signals are used to select which of the bank is accessed when transferring data from or to the
SDRAM. In the first cycle, the SDRAM memory latches the row address (nRAS low): the adequate bank
and row are activated. Next cycle, the SDRAM memory latches the column address (nCAS low): the
adequate column is activated. The address is hence decoded: memory cells are sensed by sense
amplifier and data is read from or written to output buffers.
Figure 10-52 shows a block diagram of a 512 Mbits SDRAM memory (8M x 16 x 4 banks). The data bus
DQ[15:0] has a 16-bit width. Rows are addressed through A0-A12 (8192 rows) and columns through
A0-A9 (1024 columns).
2249 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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