Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
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CAUTION
Programmers must ensure that the next command (precharge-all command) is
sent after a minimum delay of 200
m
s. Other timings, such as tRP timing
between the precharge-all command and autorefresh command, are handled
automatically by the SDRC controller depending on the timing values
programmed in the appropriate registers.
2. Set CMDCODE to 0x1 (precharge all command) to precharge all banks.
3. Set CMDCODE to 0x2 (autorefresh command). The autorefresh command is automatically generated
after a time of tRP, hence SDRC_ACTIM_CTRLA_p [17:15] TRP (where p = 0 or 1, for CS0 or CS1)
must be programmed as stated in the external memory datasheet.
4. A second autorefresh command must be programmed. Set CMDCODE to 0x2 another time.
5. Then configure the mode register
SDRC_MR_p (p = 0 or 1) with BA0 and BA1 set to 0.
Because the mode register powers up in an unknown state, it must be loaded before applying any
operational command.
When MR is reprogrammed, a suitable time must elapse before an active command is issued. The
hardware ensures this by fixing tMRD to two clock cycles. The SDRC can handle CKE as force on CKE is
released through the control module.
After VDD initialization sdrc_cke0 and sdrc_cke1 signals are forced outside the SDRC subsystem by the
control module. When the external SDRAM device is correctly initialized the control module must release
the force on these sdrc_cke signals by clearing the corresponding MUXMODE bit fields in
CONTROL.CONTROL_PADCONF_SAD2D_SBUSFLAG[18:16] and
CONTROL.CONTROL_PADCONF_SDRC_CKE1[2:0] bit fields for sdrc_cke0 and sdrc_cke1 respectively.
See
Section 10.2.5.2.2 for more information on reset behavior.
10.2.5.4.2 Read/Write Access
The commands required for a normal read/write access are automatically generated as a function of the
following:
• The read/write command
• The address bus. A10 defines precharge all
• The relevant SDRC_MR_p / SDRC_EMR2_p registers
10.2.5.4.3 Memory Power Management
10.2.5.4.3.1 Clock Enable Management
The SDRC supports two autonomous clock enable pins CKE0 and CKE1. Each CS (CS0 or CS1) has its
own CKE signal. Power management of the CS0 memory is controlled by CKE0. Power management of
the CS1 memory is controlled by CKE1. This allows the SDRAM memories associated with CS0 or CS1 to
be independently placed in power-down, deep-power-down (DPD) or self-refresh (SR) mode. This is
achieved using the manual control register SDRC.
SDRC_MANUAL_p [3:0] CMDCODE field which is
defined on a per chip select basis. Entry and exit of these low-power modes is achieved using the relevant
CMDCODE.
Once the memory associated with a CS has been powered down in deep-power-down mode it cannot be
powered up by dynamic power management features. It can only exit the low-power state through the
programming of the relevant CMDCODE. The SDRC can automatically exit other low-power modes.
2274 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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