Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
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Table 5-288. TPCC_SECRH
Address Offset 0x1044
Physical address 0x01C0 1044 Instance IVA2.2 TPCC
Description Secondary Event Clear Register (High Part):
The secondary event clear register is used to clear the status of the SERH registers.
CPU write of 1 to the SECRH.En bit clears the SERH register.
CPU write of 0 has no effect.
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
Bits Field Name Description Type Reset
31 E63 Event #63 W 0
30 E62 Event #62 W 0
29 E61 Event #61 W 0
28 E60 Event #60 W 0
27 E59 Event #59 W 0
26 E58 Event #58 W 0
25 E57 Event #57 W 0
24 E56 Event #56 W 0
23 E55 Event #55 W 0
22 E54 Event #54 W 0
21 E53 Event #53 W 0
20 E52 Event #52 W 0
19 E51 Event #51 W 0
18 E50 Event #50 W 0
17 E49 Event #49 W 0
16 E48 Event #48 W 0
15 E47 Event #47 W 0
14 E46 Event #46 W 0
13 E45 Event #45 W 0
12 E44 Event #44 W 0
11 E43 Event #43 W 0
10 E42 Event #42 W 0
9 E41 Event #41 W 0
8 E40 Event #40 W 0
7 E39 Event #39 W 0
6 E38 Event #38 W 0
5 E37 Event #37 W 0
4 E36 Event #36 W 0
3 E35 Event #35 W 0
2 E34 Event #34 W 0
1 E33 Event #33 W 0
0 E32 Event #32 W 0
Table 5-289. Register Call Summary for Register TPCC_SECRH
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
906 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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