Texas Instruments OMAP36 Series, Техническое справочное руководство

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Master code
ACK
Slave address R/W_
Data
ACK P S
1
1
1 1 1 7 N bytes
F/S mode
ACK
1
Sr
1
HS mode (current source for serial clock enabled)
F/S mode
Sr Slave address
HS mode
continues
S: Start
Sr: Repeated start
P: Stop
F/S: Fast/standard mode
HS: High-speed mode
8
i2c-008
Public Version
www.ti.com
HS I
2
C Environment
17.2.1.3.4.2 HS I
2
C Data Transfer Format in HS Mode
Figure 17-8 shows the I
2
C data transfer format in HS mode.
Figure 17-8. HS I
2
C Data Transfers in HS Mode
Each HS I
2
C controller module can also operate in HS mode. In this case, after the S condition, the
module, which is in F/S mode, writes the master code address (000001XXX, where XXX is the variable
portion of the master code) on the bus. No device connected on the same bus acknowledges this address.
The module switches the clock to the HS clock and after an Sr condition, and sends the slave address
and the data, as shown in
Figure 17-8 .
NOTE: For more information, see I
2
C Bus Specification v2.1, January 2000.
17.2.1.3.5 HS I
2
C Master Transmitter Mode
In master transmitter mode, data assembled in one of the previously described data formats is shifted out
on serial data line i2ci_sda in synchronization with the self-generated clock pulses on serial clock line
i2ci_scl. When the intervention of the processor is required (the I2Ci.
I2C_STAT [10] XUDF bit) after a byte
is transmitted, the clock pulses are inhibited and the serial clock line is held low.
17.2.1.3.6 HS I
2
C Master Receiver Mode
Master receiver mode can be entered only from master transmitter mode. With any of the address formats
(a), (b), or (c) (see
Figure 17-7 ), if the R/W_ bit is high, the module enters master receiver mode after the
slave address byte and bit R/W_ are transmitted. Serial data bits received on bus line i2ci_sda are shifted
in synchronization with the self-generated clock pulses on i2ci_scl. When the intervention of the processor
is required (the I2Ci.
I2C_STAT [11] ROVR bit) after a byte is transmitted, the clock pulses are inhibited and
the serial clock line is held low. At the end of a transfer, a P condition is generated.
17.2.1.3.7 HS I
2
C Slave Transmitter Mode
Slave transmitter mode can be entered only from slave receiver mode. With any of the address formats
(a), (b), or (c) (see
Figure 17-7 ), slave transmitter mode is entered if the slave address byte is the same
as its own address, and when the R/W_ bit transmitted by the master transmitter is high. The slave
transmitter shifts the serial data out on data line i2ci_sda in synchronization with the clock pulses
generated by the master device. It does not generate the clock, but it can hold clock line i2ci_scl low when
intervention of the LH is required (the I2Ci.
I2C_STAT [10] XUDF bit).
17.2.1.3.8 HS I
2
C Slave Receiver Mode
In slave receiver mode, serial data bits received on bus line i2ci_sda are shifted in synchronization with
the clock pulses on i2ci_scl generated by the master device. The slave receiver does not generate the
clock, but it can hold the serial clock line low when intervention of the LH is required (the
I2Ci.
I2C_STAT [11] ROVR bit) after a byte is received.
2773 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated