Texas Instruments OMAP36 Series, Техническое справочное руководство

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L3 Interconnect
Table 9-94. L3_PM_ADDR_MATCH_k
Address Offset 0x060 + (0x20+k) Index k = 1 to 1 for PM_RT
k = 1 to 7 for PM_GPMC
k = 1 to 1 for PM_OCM_ROM
k = 1 to 3 for PM_IVA2
k = 1 to 7 for PM_OCM_RAM
Physical Address See Table 9-75 to Table 9-77
Description
Type R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BASE_ADDR SIZE
LEVEL
Reserved
ADDR_SPACE
Bits Field Name Description Type Reset
63:20 Reserved Reserved R 0x00000000000
19:10 BASE_ADDR Protection region base address R see Table 9-96
9 LEVEL Protection region level. R see Table 9-96
8 Reserved Reserved R 0
7:3 SIZE Protection region size R see Table 9-96
2:0 ADDR_SPACE Protection region address space R see Table 9-96
Table 9-95. Register Call Summary for Register L3_PM_ADDR_MATCH_k
L3 Interconnect
• Protection Region : [0] [1] [2]
• Priority Level Overview : [3] [4] [5]
• L3 Firewall Registers Overview : [6] [7] [8]
• Typical Example of Firewall Programming Example : [9] [10] [11] [12] [13]
• Protection Mechanism (PM) : [14] [15] [16]
2051 SWPU177N – December 2009 – Revised November 2010 Interconnect
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