Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 1821 / 3738

Public Version
www.ti.com
Display Subsystem Register Manual
Bits Field Name Description Type Reset
1 DSI_CLK_SWITCH Selects the clock source for the DSI functional clock RW 0
0x0: DSS1_ALWON_FCLK clock is selected (from
PRCM)
0x1: DSI2_PLL_FCLK clock is selected (from DSI PLL)
0 DISPC_CLK_SWITCH Selects the clock source for the DISPC functional clock RW 0
0x0: DSS1_ALWON_FCLK clock is selected (from
PRCM)
0x1: DSI1_PLL_FCLK clock is selected (from DSI PLL)
Table 7-135. Register Call Summary for Register DSS_CONTROL
Display Subsystem Environment
• TV Display Support : [0]
• Digital-to-Analog Converters : [1]
Display Subsystem Integration
• Clocks : [2] [3] [4] [5] [6] [7]
Display Subsystem Functional Description
• Video Encoder Functionalities : [8]
• Video DAC Stage Power Management : [9] [10]
Display Subsystem Basic Programming Model
• Display Subsystem Configuration Phase : [11] [12] [13] [14]
• Video DAC Stage Settings : [15]
Display Subsystem Use Cases and Tips
• Display Subsystem Clock Configuration : [16] [17] [18]
• DPLL4 in Low-Power Mode : [19] [20]
• Switch to DSI PLL Clock Source : [21]
• Switch to DSI PLL Clock Source : [22] [23]
Display Subsystem Register Manual
• Display Subsystem Register Mapping Summary : [24]
Table 7-136. DSS_CLK_STATUS
Address Offset 0x05C
Physical address 0x4805 005C Instance DISS
Description This register contains the display subsystem register.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
DSI_PLL_CLK2_STATUS DSI_PLL_CLK1_STATUS
DSS_DSI_CLK1_STATUS
DSS_DISPC_CLK1_STATUS
Bits Field Name Description Type Reset
31:9 RESERVED RESERVED R 0x0000000
8 DSI_PLL_CLK2_ DSI2_PLL_FCLK clock selection status (DSI mux) Indicates if R 0
STATUS the DSI protocol engine is running from the DSI2_PLL_FCLK
clock
Read 0: DSI2_PLL_FCLK is not selected (unused by DSI).
Read 1: DSI2_PLL_FCLK is selected (used by DSI).
1821 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated