Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Basic Programming Model
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NOTE:
• The REGM3 and REGM4 factors must according with the following conditions:
– The DSI1_PLL_FCLK and DSI2_PLL_FCLK frequencies must be a multiple of the
PCLK frequency (for proper settings of PCD and LCD factors in the DISPC).
– The DSI1_PLL_FCLK and DSI2_PLL_FCLK frequencies must be lower than 173
MHz at nominal voltage (OPP100), and lower than 100 MHz at low voltage
(OPP50).
• Most of the other DSI PLL programming values are available for software flexibility but it
is not recommended to update the values in normal use. See
Section 7.5.5.7 for details
on DSI PLL recommended values.
DSI PLL programming examples:
•
WVGA Display on one data pair: Pixel clock (PCLK) = 30 MHz with 18-BPP pixel format
The data rate is 30 × 18 = 540 Mbps on one data lane. Therefore, the frequency on the data lane is twice
the data rate: 1080 MHz.
The frequency on the clock lane is 270 MHz (1080 divided by 4).
The SYS_CLK at 26 MHz is selected as the clock reference by setting the
DSS.
DSI_PLL_CONFIGURATION2 [11] DSI_PLL_CLKSEL to 0b0.
Set the DSS. DSI_PLL_CONFIGURATION2 [12] DSI_PLL_HIGHFREQ to 0b0 as PCLK is lower than 32
MHz.
Set Fint to 2 MHz as PLL internal reference frequency: Set REGN to 12 (divide by 13) by setting the
DSS.
DSI_PLL_CONFIGURATION1 [7:1] DSI_PLL_REGN bit field to 0xC.
To get the CLKIN4DDR to 1080 MHz, set the REGM factor to 270 by setting the
DSS.
DSI_PLL_CONFIGURATION1 [18:8] DSI_PLL_REGM to 0x10E.
DSI_PHY = 2 x 270/13 x 26/1 = 1080 MHz
Because DSI1_PLL_FCLK and DSI2_PLL_FCLK (REGM3 and REGM4 factors) must be multiples of
PCLK and also lower than 173 MHz at nominal voltage (OPP100), and lower than 100 MHz at low voltage
(OPP50), program these frequencies to 90 MHz by setting the REGM3 and REGM4 factors to 11 (divide
by 12). This is done by setting the DSS.
DSI_PLL_CONFIGURATION1 [22:19] DSS_CLOCK_DIV bit field
and DSS. DSI_PLL_CONFIGURATION1 [26:23] DSIPROTO_CLOCK_DIV to 0xB:
DSI1_PLL_FCLK = DSI2_PLL_FCLK = 1080/12 = 90 MHz
• XGA Display on two data pairs: Pixel clock (PCLK) = 60 MHz with 16-BPP pixel format
The data rate is (60 × 16)/2 = 480 Mbps on each data lane. Therefore, the frequency on the data lane
is twice the data rate: 960 MHz.
The frequency on the clock lane is 240 MHz (960 divided by 4).
The SYS_CLK at 26 MHz is selected as the clock reference by setting the
DSS.
DSI_PLL_CONFIGURATION2 [11] DSI_PLL_CLKSEL bit to 0b0.
Set the DSS. DSI_PLL_CONFIGURATION2 [12] DSI_PLL_HIGHFREQ bit to 0b0 as the source clock
frequency (SYS_CLK in this example) is lower than 32 MHz.
Set Fint to 2 MHz as PLL internal reference frequency: Set REGN to 12 (divide by 13) by setting the
DSS.
DSI_PLL_CONFIGURATION1 [7:1] DSI_PLL_REGN bit field to 0xC.
To get the CLKIN4DDR to 960 MHz, set the REGM factor to 240 by setting the
DSS.
DSI_PLL_CONFIGURATION1 [18:8] DSI_PLL_REGM to 0x0F0.
DSI_PHY = 2 × 240/13 × 26/1 = 960 MHz
Because DSI1_PLL_FCLK and DSI2_PLL_FCLK (REGM3 and REGM4 factors) must be multiples of
PCLK and also lower than 173 MHz at nominal voltage (OPP100), program these frequencies to 120
MHz by setting the REGM3 and REGM4 factors to 7 (divide by 8). This is done by setting the
DSS.
DSI_PLL_CONFIGURATION1 [22:19] DSS_CLOCK_DIV bit field and
DSS. DSI_PLL_CONFIGURATION1 [26:23] DSIPROTO_CLOCK_DIV to 0x7:
DSI1_PLL_FCLK = DSI2_PLL_FCLK = 960/8 = 120 MHz
1756 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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