Public Version
IVA2.2 Subsystem Register Manual
www.ti.com
Table 5-438. Register Call Summary for Register TPTCj_PBIDX
IVA2.2 Subsystem Functional Description
•
:
IVA2.2 Subsystem Register Manual
•
TPTC0 and TPTC1 Register Mapping Summary
Table 5-439. TPTCj_PMPPRXY
Address Offset
0x214
Physical address
0x01C1 0214
Instance
IVA2.2 TPTC0
Physical address
0x01C1 0614
Instance
IVA2.2 TPTC1
Description
Prog Set Mem Protect Proxy
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
PRIVID
PRIV
Bits
Field Name
Description
Type
Reset
31:9
Reserved
Read returns 0.
R
0x000000
8
PRIV
Privilege Level:
R
0
PRIV = 0: User level privilege
PRIV = 1: Supervisor level privilege
PMPPRXY.PRIV is always updated with the value from the
configuration bus Privilege field on any/every write to Program Set
BIDX Register (trigger register). The PRIV value for the SA Set and
DF Set are copied from the value in the Program set along with the
remainder of the parameter values. The privilege ID is issued on the
VBusM read and write command bus such that the target endpoints
can perform memory protection checks based on the PRIV of the
external host that sets up the DMA transaction.
7:4
Reserved
Read returns 0.
R
0x0
3:0
PRIVID
Privilege ID:
R
0x0
PMPPRXY.PRIVID is always updated with the value from
configuration bus Privilege ID field on any/every write to Program Set
BIDX Register (trigger register). The PRIVID value for the SA Set
and DF Set are copied from the value in the Program set along with
the remainder of the parameter values. The privilege ID is issued on
the VBusM read and write command bus such that the target
endpoints can perform memory protection checks based on the
privid of the external host that sets up the DMA transaction.
Table 5-440. Register Call Summary for Register TPTCj_PMPPRXY
IVA2.2 Subsystem Functional Description
•
:
IVA2.2 Subsystem Register Manual
•
TPTC0 and TPTC1 Register Mapping Summary
968
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...