Texas Instruments OMAP36 Series, Техническое справочное руководство

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McSPI Register Manual
Bits Field Name Description Type Reset
Read 0x0: FIFO Receive Buffer is not empty
Read 0x1: FIFO Receive Buffer is empty
4 TXFFF Channel x FIFO Transmit Buffer Full Status R 0x0
Read 0x0: FIFO Transmit Buffer is not full
Read 0x1: FIFO Transmit Buffer is full
3 TXFFE Channel x FIFO Transmit Buffer Empty Status R 0x0
Read 0x0: FIFO Transmit Buffer is not empty
Read 0x1: FIFO Transmit Buffer is empty
2 EOT Channel x end-of-transfer status. The definitions of beginning and R 0x0
end of transfer vary with master versus slave and the transfer
format (transmit/receive mode, turbo mode). See dedicated
chapters for details.
Read 0x0: This flag is automatically cleared when the
shift register is loaded with the data from the
MCSPI_TXx register (beginning of transfer).
Read 0x1: This flag is automatically set to one at the end
of an SPI transfer.
1 TXS Channel x MCSPI_TXx register status R 0x0
Read 0x0: Register is full.
Read 0x1: Register is empty.
0 RXS Channel x MCSPI_RXx register status R 0x0
Read 0x0: Register is empty.
Read 0x1: Register is full.
Table 20-39. Register Call Summary for Register MCSPI_CHxSTAT
McSPI Functional Description
• Master Transmit-and-Receive Mode (Full Duplex) : [0] [1] [2]
• Master Transmit-Only Mode (Half Duplex) : [3]
• Master Receive-Only Mode (Half Duplex) : [4]
• Single-Channel Master Mode : [5] [6] [7] [8] [9]
• Dedicated Resources : [10] [11]
• Slave Transmit-and-Receive Mode : [12]
• Slave Transmit-Only Mode : [13]
• Slave Receive-Only Mode : [14]
• End of Transfer Management : [15]
McSPI Register Manual
• McSPI Register Summary : [16]
3049 SWPU177N – December 2009 – Revised November 2010 Multichannel SPI
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