Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Functional Description
• 256b read buffer to prefetch a read line from which the burst is read
These buffers are completely decoupled; writes use the write buffer and reads use the read buffer. This is
not a data cache, as there is no load-forwarding from the write buffer, and no prefetch buffer to be
updated by an incoming write.
NOTE: There is no concept of dirty bit and write-back policy.
5.3.5.2 Arbiter
The arbiter allows the three modules (iME, iLF, BWO) to access L2 memory without taking care of
concurrent access themselves. No bubble is introduced by the arbitration, which means that when a
request is initiated by the iME, the iLF, or the BWO, a request is transmitted to the SL2. This arbitration
ensures 100 percent bandwidth use. The arbitration is fair and does not starve an initiator for more than
three cycles.
To return data to the correct initiator, the arbiter keeps track of the ordering of memory requests
committed to the SL2 memory interface.
The SL2 memory interface can sustain a 2x16-byte request per SL2 memory interface clock cycle,
whether the request is a read or write or interleaved reads and writes, and regardless of which module
generates the request (iME, iLF, or local interconnect port initiators), if the initiator is not preempted by the
others (no competition) and provides an equivalent input throughput.
5.3.5.3 Restrictions on SL2 Memory Usage
Because accesses to SL2 (from iME, iLF, or any other initiator with access to the SL2IF interface) are not
checked for access permission, the SL2 memory must not be used for memory-protected or sensitive
data.
SL2 memory must not be used to store sequencer instructions to be fetched directly by the sequencer; the
SL2IF is not designed to efficiently serve sequencer instruction fetches. SL2 memory can hold sequencer
instructions, but they must be transferred by the EDMA module into the ITCM before being executed.
5.3.5.4 Error Management
The SL2 memory interface responds to the following conditions with an in-band error (SResp = ERR):
• Nonaligned address (MAddr[1:0] <>0)
• Unsupported command (MCmd not belonging to READ/WR/WRNP)
All valid accesses are propagated to the SL2 memory interface; the address must always be mapped in
SL2.
5.3.6 Wake-Up Generator
The wake-up generator (WUGEN) controls the following:
• Implementing the IVA2.2 idle handshake protocol with the PRCM
• Resynchronizing interrupts and DMA requests from device peripherals external to the IVA2.2
subsystem
• Blocking the interrupts and DMA requests to the IVA2.2 on clean boundaries, when the WUGEN is
asked to go into IDLE state
• Detecting the enabled wake-up interrupts and DMA requests and generating a wake-up event to the
PRCM
• Formatting interrupts to DSP megamodule interrupt format
Figure 5-19 shows the WUGEN in the IVA2.2 subsystem and its interactions with other submodules.
733 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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