Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
10.1.5.3.8.1 Access Time on Read Access
In asynchronous read mode, for single and paged accesses, RDACCESSTIME field (i = 0 to 7) defines
the number of GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge used for the
first data capture. RDACCESSTIME must be programmed to the rounded greater GPMC_FCLK cycle
value of the read access time of the attached memory device.
In synchronous read mode, for single or burst accesses, RDACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge corresponding to the
GPMC_CLK rising edge used for the first data capture.
GPMC_CLK which is sent to the memory device for synchronization with the GPMC controller, is internally
retimed to correctly latch the returned data. RDCYCLETIME must be greater than RDACCESSTIME in
order to let the GPMC latch the last return data using the internally retimed GPMC_CLK.
The external WAIT signal can be used in conjunction with RDACCESSTIME to control the effective GPMC
data-capture GPMC_FCLK edge on read access in both asynchronous mode and synchronous mode. For
details about wait monitoring, see
Section 10.1.5.4 .
10.1.5.3.8.2 Access Time on Write Access
In asynchronous write mode, the GPMC_CONFIG6_i [28:24] WRACCESSTIME timing parameter is not
used to define the effective write access time. Instead, it is used as a WAIT invalid timing window, and
must be set to a correct value so that the gpmc_wait pin is at a valid state two GPMC_CLK cycles before
WRACCESSTIME completes. For details about wait monitoring, see
Section 10.1.5.4 .
In synchronous write mode , for single or burst accesses, WRACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_CLK rising edge used by the memory device for
the first data capture.
The external WAIT signal can be used in conjunction with WRACCESSTIME to control the effective
memory device data capture GPMC_CLK edge for a synchronous write access. For details about wait
monitoring, see
Section 10.1.5.4 .
10.1.5.3.9 Page Burst Access Time (PAGEBURSTACCESSTIME)
PAGEBURSTACCESSTIME is programmed in the GPMC. GPMC_CONFIG5_i [27:24] bit field (i = 0 to 7).
PAGEBURSTACCESSTIME can be set from 0 to 15 GPMC_FCLK cycles with a granularity of one
(GPMC.
GPMC_CONFIG1_i [4] TIMEPARAGRANULARITY set to 0), or from 0 to 30 GPMC_FCLK cycles
with a granularity of two (TIMEPARAGRANULARITY set to 1).
10.1.5.3.9.1 Page Burst Access Time on Read Access
In asynchronous page read mode, the delay between successive word captures in a page is controlled
through the PAGEBURSTACCESSTIME bit field. The PAGEBURSTACCESSTIME parameter must be
programmed to the rounded greater GPMC_FCLK cycle value of the read access time of the attached
device.
In synchronous burst read mode, the delay between successive word captures in a burst is controlled
through the PAGEBURSTACCESSTIME field.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective GPMC data capture GPMC_FCLK edge on read access. For details about wait monitoring, see
Section 10.1.5.4 .
10.1.5.3.9.2 Page Burst Access Time on Write Access
Asynchronous page write mode is not supported. PAGEBURSTACCESSTIME is irrelevant in this case.
In synchronous burst write mode, PAGEBURSTACCESSTIME controls the delay between successive
memory device word captures in a burst.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective memory-device data capture GPMC_CLK edge in synchronous write mode. For details about
wait monitoring, see
Section 10.1.5.4 .
2133 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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