Texas Instruments OMAP36 Series, Техническое справочное руководство

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Display Subsystem Register Manual
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Table 7-276. RFBI_DATA_CYCLE3_i
Address Offset 0x74+ (i* 0x18) Index i = 0 to 1
Physical address 0x4805 0874+ (i* 0x18) Instance RFBI
Description The control register configures the RFBI data format for 3rd cycle.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved NBBITSPIXEL2 Reserved Reserved NBBITSPIXEL1
BITALIGNMENTPIXEL2 BITALIGNMENTPIXEL1
Bits Field Name Description Type Reset
31:28 Reserved Write 0s for future compatibility RW 0x0
Read returns 0
27:24 BITALIGNMENTPIXEL2 Bit alignment RW 0x0
Alignment of the bits from pixel#2 on the output interface
23:21 Reserved Write 0s for future compatibility RW 0x0
Read returns 0
20:16 NBBITSPIXEL2 Number of bits RW 0x00
Number of bits from the pixel #2 (value from 0 to16 bits).
The values from 17 to 31 are invalid.
15:12 Reserved Write 0s for future compatibility RW 0x0
Read returns 0
11:8 BITALIGNMENTPIXEL1 Bit alignment RW 0x0
Alignment of the bits from pixel#1 on the output interface
7:5 Reserved Write 0s for future compatibility RW 0x0
Read returns 0
4:0 NBBITSPIXEL1 Number of bits RW 0x00
Number of bits from the pixel #1 (value from 0 to16 bits).
The values from 17 to 31 are invalid.
Table 7-277. Register Call Summary for Register RFBI_DATA_CYCLE3_i
Display Subsystem Functional Description
• Output Parallel Modes : [0]
Display Subsystem Basic Programming Model
• Cycle Format : [1]
Display Subsystem Register Manual
• RFBI Register Mapping Summary : [2]
1880 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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