Texas Instruments OMAP36 Series, Техническое справочное руководство

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McBSP Basic Programming Model
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NOTE:
• The necessary duration of the active-low period of XRST or RRST is at least two
CLKR/CLKX cycles.
• The appropriate bits in serial port configuration registers
(McBSPi.
MCBSPLP_SPCR1_REG , McBSPi. MCBSPLP_SPCR2_REG ,
McBSPi. MCBSPLP_PCR_REG , McBSPi. MCBSPLP_RCR1_REG ,
McBSPi. MCBSPLP_RCR2_REG , McBSPi. MCBSPLP_XCR1_REG ,
McBSPi. MCBSPLP_XCR2_REG , McBSPi. MCBSPLP_THRSH2_REG ,
McBSPi. MCBSPLP_XCCR_REG , McBSPi. MCBSPLP_SYSCONFIG_REG ,
McBSPi. MCBSPLP_SRGR1_REG , and McBSPi. MCBSPLP_SRGR2_REG ) should only
be modified when the affected portion of the serial port is in its reset state.
• In most cases, the data transmit register (McBSPi. MCBSPLP_DXR_REG ) should be
loaded by the MPU/IVA2 subsystem or the sDMA controller only when the transmitter is
enabled (McBSPi.
MCBSPLP_SPCR2_REG [0] XRST = 1). An exception to this rule is
when these registers are used for loopback internal data.
• The bits of the channel control registers (McBSPi. MCBSPLP_MCR1_REG ,
McBSPi. MCBSPLP_MCR2_REG , McBSPi.MCBSPLP_RCER{A-H}_REG and
McBSPi.MCBSPLP_XCER{A-H}_REG) can be modified at any time as long as they are
not being used by the current reception/transmission in a multichannel selection mode.
• The SRG is reset by setting McBSPi. MCBSPLP_SPCR2_REG [6] GRST bit to 0.
• It is not necessary to wait if SRG is not used.
• Modification on-the-fly has no effect if a reset is not done first.
21.5.1.2 Reset and Initialization Procedure for the Sample Rate Generator
To reset and initialize the Sample Rate Generator:
• Place the McBSP Sample Rate Generator in RESET.
During a Global RESET, the Sample Rate Generator, the Receiver, and the Transmitter reset bits
(GRST, RRST, and XRST) are automatically forced to '0'. Otherwise, during normal operation, the
Sample Rate Generator can be reset by making McBSPi.
MCBSPLP_SPCR2_REG [6] GRST=0,
provided that CLKG and/or FSG internal signal is not used by any portion of the McBSP module.
Depending on the system needs, the software may also to reset the Receiver
(McBSPi.
MCBSPLP_SPCR1_REG [0] RRST=0) and reset the Transmitter
(McBSPi. MCBSPLP_SPCR2_REG [0] XRST bit =0).
• Program the registers that affect the Sample Rate Generator.
Program the Sample Rate Generator registers (McBSPi.
MCBSPLP_SPCR1_REG and
McBSPi. MCBSPLP_SPCR2_REG ) as required for your application. Refer to Figure 21-59 .
If necessary, other control registers can be loaded with desired values provided the respective portion
of the McBSP module (the Receiver or Transmitter) is in reset.
Table 21-24 presents the McBSP
configuration when one of the clock sources is selected, but others registers can be impacted in
function of the user application.
Table 21-24. McBSP Configuration in Function of the SRG Clock Source Selected
McBSPi. MCBSPLP_PCR_REG Configuration
SRG Clock Source Module
Selected Configuration
CLKRM bit
(1)
CLKXM bit FSRM bit
(1)
FSXM bit
Master Transmitter
0 1 0 1
and Slave Receiver
McBSPi_ICLK
Master Receiver and
or 1 0 1 0
Slave Transmitter
CLKS
Master Transmitter
1 1 1 1
and Receiver
Master Transmitter
CLKR 0 1 0 1
and Slave Receiver
CLKX Master Receiver and
1 0 1 0
Slave Transmitter
(1)
This configuration is correct if McBSPi.MCBSPLP_XCCR_REG[5] DLB bit=0x0. When the DLB bit is set to 1, the CLKR clock (not the
mcbspi_clkr pin) is driven by the CLKX clock, which is based on the CLKXM bit.
3128 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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