Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Memory Controller
10.1.5.14.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
The GPMC. GPMC_CONFIG7_i register (where i = 0 to 7) associated with a NAND device region
interfaced in byte or word stream mode can be initialized with a minimum size of 16 Mbytes, because any
address location in the chip-select memory region can be used to access a NAND data array. The NAND
Flash protocol specifies an address sequence where address bits are passed through the data bus in a
series of write accesses with the ALE pin asserted. After this address phase, all operations are streamed
and the system requests address is irrelevant.
CAUTION
To allow correct command, address, and data-access controls, the
GPMC. GPMC_CONFIG1_i register associated with a NAND device region
must be initialized in asynchronous read and write modes with the parameters
listed in
Table 10-4 . Failure to comply with these settings corrupts the NAND
interface protocol.
Table 10-4. Chip-Select Configuration for NAND Interfacing
Bit Field Register Value Comments
WRAPBURST GPMC_CONFIG1_i [31]
(1)
0 No wrap
READMULTIPLE GPMC_CONFIG1_i [30] 0 Single access
READTYPE GPMC_CONFIG1_i [29] 0 Asynchronous mode
WRITEMULTIPLE GPMC_CONFIG1_i [28] 0 Single access
WRITETYPE GPMC_CONFIG1_i [27] 0 Asynchronous mode
CLKACTIVATIONTIME GPMC_CONFIG1_i [26:25] 00
ATTACHEDDEVICEPAGELENGTH GPMC_CONFIG1_i [24:23] Don't Single-access mode
care
WAITREADMONITORING GPMC_CONFIG1_i [22] 0 Wait not monitored by GPMC access
engine
WAITWRITEMONITORING GPMC_CONFIG1_i [21] 0 Wait not monitored by GPMC access
engine
WAITMONITORINGTIME GPMC_CONFIG1_i [19:18] Don't Wait not monitored by GPMC access
care engine
WAITPINSELECT GPMC_CONFIG1_i [17:16] Select which wait is monitored by edge
detectors
DEVICESIZE GPMC_CONFIG1_i [13:12] 0b00 or 8- or 16-bit interface
0b01
DEVICETYPE GPMC_CONFIG1_i [11:10] 0b10 NAND device in stream mode
MUXADDDATA GPMC_CONFIG1_i [9] 0 Nonmultiplexed mode
TIMEPARAGRANULARITY GPMC_CONFIG1_i [4] 0 Timing achieved with best GPMC clock
granularity
GPMCFCLKDIVIDER GPMC_CONFIG1_i [1:0] Don't Asynchronous mode
care
(1)
i = 0 to 7
The GPMC. GPMC_CONFIG1_i to GPMC. GPMC_CONFIG4_i register (where i = 0 to 7) associated with a
NAND device region must be initialized with the correct control-signal timing value according to the NAND
device timing parameters.
10.1.5.14.1.2 NAND Device Command and Address Phase Control
NAND devices require multiple address programming phases. The CPU software driver is responsible for
issuing the correct number of command and address program accesses, according to the device
command set and the device address-mapping scheme.
2157 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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