Public Version
Display Subsystem Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
31:29
REG_TTAGO
TTA-GO timing in terms of number of TXCLKESC clocks
RW
0x2
0x0: 2 cycles
0x1: 3 cycles
0x2: 4 cycles
0x3: 5 cycles
0x4: 6 cycles
0x5: 7 cycles
0x6: 8 cycles
0x7: 9 cycles
Default value: 4 cycles
28:27
REG_TTASURE
TTA-SURE timing in terms of number of TXCLKESC clocks
RW
0x0
0x0: 2 cycles
0x1: 1 cycle
0x2: 3 cycles
0x3: 4 cycles
Default value: 2 cycles
26:24
REG_TTAGET
TTA-GET timing in terms of number of TXCLKESC clocks
RW
0x2
0x0: 3 cycles
0x1: 4 cycles
0x2: 5 cycles
0x3: 6 cycles
0x4: 7 cycles
0x5: 8 cycles
0x6: 9 cycles
0x7: 10 cycles
Default value: 5 cycles
23:21
RESERVED
Reserved.
R
0x0
20:16
REG_TLPXBY2
(TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR
RW
0x0A
clock = CLKIN4DDR/4.
PROGRAMMED VALUE = ceil (25 ns / DDR_Clock_Period).
Actual value seen on line:
N = REG_TLPXBY2 = ceil (2 * N/4) * 4 * DDR_Clock_Period
Default value is programmed for 400 MHz
This is the internal timer value. The value seen on line will have variance
due to rise/fall mismatch effects.
Note: TLPX is used to define the length of LP-01 state in HS Start of
Transmission sequences on clock and data lanes. For all other purposes
TLPX is defined by the period of TxLPEsc clock.
15:8
REG_TCLKTRAIL
REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency.
RW
0x1A
DDR clock = CLKIN4DDR/4.
D-PHY specification: > 60 ns
Actual value seen on line:
N = REG_TCLKTRAIL = {ceil[(N + 3)/4] * 4 – 1.5} * DDR_Clock_
(~ 0 ns --- 5 ns)
PROGRAMMED VALUE = ceil (60 ns / DDR_Clock_Period) + 2
Default value is programmed for 400 MHz.
7:0
REG_TCLKZERO
REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR
RW
0x6A
clock = CLKIN4DDR/4.
D-PHY specification: (REG_TCLKP REG_TCLKZERO) > 300
ns
Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE =
38 ns): REG_TCLKZERO > 262 ns
1954
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...