Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Functional Description
Table 3-12. CORE Power Domain Reset Signals (continued)
Name I/O
(1)
Source/Destination
(2)
Reset Domain
USBTLL_RST I PRM Resets the USB TLL asynchronously
The CM logic is reset on:
• Any global cold reset
• A CORE power domain transition from off to on
Because the CM logic is not reset in this case, CM registers that are sensitive to a warm reset must also
be reset synchronously with the L4 clock when a global warm reset occurs.
3.5.1.5.5 DSS Power Domain
The DSS power domain has one reset input signal (see Table 3-13 ).
Table 3-13. DSS Power Domain Reset Signal
Name I/O
(1)
Source Reset Domain
DSS_RST I PRM Resets the entire display subsystem
(1)
I = Input; O = Output
3.5.1.5.6 CAM Power Domain
The CAM power domain has one reset input signal (see Table 3-14 ).
Table 3-14. CAM Power Domain Reset Signal
Name I/O
(1)
Source Reset Domain
CAM_RST I PRM Resets the entire camera subsystem
(1)
I = Input; O = Output
3.5.1.5.7 USBHOST Power Domain
The USBHOST power domain has one reset input signal (see Table 3-15 ).
Table 3-15. USBHOST Power Domain Reset Signal
Name I/O
(1)
Source Reset Domain
USBHOST_RST I PRM Resets the entire HS USB host
subsystem
(1)
I = Input; O = Output
3.5.1.5.8 SGX Power Domain
The SGX power domain has one reset input signal (see Table 3-16 ).
Table 3-16. SGX Power Domain Reset Signal
Name I/O
(1)
Source Reset Domain
SGX_RST I PRM Resets the entire SGX subsystem
(1)
I = Input, O = Output
3.5.1.5.9 WKUP Power Domain
The WKUP power domain has three reset input signals and two reset output signals (see Table 3-17 ).
257 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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