Texas Instruments OMAP36 Series, Техническое справочное руководство

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SCM Register Manual
Table 13-83. CONTROL_PADCONF_CAPABILITIES (continued)
REGISTER NAME Pad name Physical address WakeUpx Off Mode Input Reserved PU/PD MuxMode
Enable
CONTROL_PADCONF_CSI2_DX1[15:0] csi2_dx1 0x48002138 0b00 0b00--0 0b1 0b000 0b01 0b111
CONTROL_PADCONF_CSI2_DX1[31:16] csi2_dy1 0x48002138 0b00 0b00--0 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP2_FSX[15:0] mcbsp2_fsx 0x4800213C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP2_FSX[31:16] mcbsp2_clkx 0x4800213C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP2_DR[15:0] mcbsp2_dr 0x48002140 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP2_DR[31:16] mcbsp2_dx 0x48002140 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_CLK[15:0] sdmmc1_clk 0x48002144 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_CLK[31:16] sdmmc1_cmd 0x48002144 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_DAT0[15:0] sdmmc1_dat0 0x48002148 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_DAT0[31:16] sdmmc1_dat1 0x48002148 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_DAT2[15:0] sdmmc1_dat2 0x4800214C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC1_DAT2[31:16] sdmmc1_dat3 0x4800214C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC2_CLK[15:0] sdmmc2_clk 0x48002158 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC2_CLK[31:16] sdmmc2_cmd 0x48002158 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_MMC2_DAT0[15:0] sdmmc2_dat0 0x4800215C 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_MMC2_DAT0[31:16] sdmmc2_dat1 0x4800215C 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_MMC2_DAT2[15:0] sdmmc2_dat2 0x48002160 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_MMC2_DAT2[31:16] sdmmc2_dat3 0x48002160 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_MMC2_DAT4[15:0] sdmmc2_dat4 0x48002164 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC2_DAT4[31:16] sdmmc2_dat5 0x48002164 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC2_DAT6[15:0] sdmmc2_dat6 0x48002168 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MMC2_DAT6[31:16] sdmmc2_dat7 0x48002168 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP3_DX[15:0] mcbsp3_dx 0x4800216C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP3_DX[31:16] mcbsp3_dr 0x4800216C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP3_CLKX[15:0] mcbsp3_clkx 0x48002170 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_MCBSP3_CLKX[31:16] mcbsp3_fsx 0x48002170 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_UART2_CTS[15:0] uart2_cts 0x48002174 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_UART2_CTS[31:16] uart2_rts 0x48002174 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_UART2_TX[15:0] uart2_tx 0x48002178 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_UART2_TX[31:16] uart2_rx 0x48002178 0b00 0b00000 0b1 0b000 0b11 0b111
CONTROL_PADCONF_UART1_TX[15:0] uart1_tx 0x4800217C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_UART1_TX[31:16] uart1_rts 0x4800217C 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_UART1_CTS[15:0] uart1_cts 0x48002180 0b00 0b00000 0b1 0b000 0b01 0b111
2561 SWPU177N – December 2009 – Revised November 2010 System Control Module
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