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IVA2.2 Subsystem Basic Programming Model
3
2
2
2
2
2
1
1
1
1
1
6
5
4
3
2
1
0
1
9
8
7
3
2
8
7
3
2
1
0
0
0
0
dst
src2
0
1
1
0
1
0
1
1
1
1
0
0
1
0
0
0
s
p
Opcode map field used…
For operand type…
Unit
src2
ucst5
.S1,.S2
dst
ucst5
Opcode:
.M Unit
3
2
2
2
2
2
1
1
1
1
1
6
5
4
3
2
1
0
1
9
8
7
3
2
8
7
3
2
1
0
0
0
0
dst
src2
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
s
p
Opcode map field used…
For operand type…
Unit
src2
ucst5
.M1,.M2
dst
ucst5
Description:
A 10-bit data value is sent to the EFI. The five most-significant bits (MSBs) of the 10-bit
value are taken from dst; the five least-significant bits (LSBs) are taken from src2. There
is an A-side EFI and a B-side EFI. The side used is determined by the S unit that is
selected.
This instruction executes unconditionally; that is, it cannot be predicated. The EFCMD
instruction does not use any data path resources. It is available for scheduling purposes
on the S or M units. Only one EFCMD instruction can be scheduled per side; the S or M
slot on a side can be used, but not both in the same execute packet. If used in an
SPLOOP body, the EFCMD instruction occupies an execution slot corresponding to the
unit specified.
The 10-bit command is output at the CPU boundary in E2. The ready signal is not
sampled in conjunction with the EFCMD instruction.
Execution:
if(.S1)
ucst10
→
A_EFI_Cmd[9:0]
else if(.S2)
ucst10
→
B_EFI_Cmd[9:0]
else if(.M1)
ucst10
→
A_EFI_Cmd[9:0]
else if(.M2)
ucst10
→
B_EFI_Cmd[9:0]
Instruction type:
Single-cycle
Delay slots:
0
EFRDW
Receive Double Word From EFI
Syntax:
EFRDW (.unit) dst_o:dst_e
.unit = .S1, .S2
Compatibility:
C64x+ CPU only
Opcode:
3
2
2
2
2
2
1
1
1
1
1
6
5
4
3
2
1
0
1
9
8
7
3
2
8
7
3
2
1
0
0
0
0
dst
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
1
0
0
0
s
p
767
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
