Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Register Manual
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Bits Field Name Description Type Reset
31:15 RESERVED Write 0s for future compatibility. RW 0x00000
Reads returns 0.
14 FIINV Field identification signal inverse RW 0x0
This bit field is latched by the VS sync pulse.
0x0: Non inverse
0x1: Inverse
13:12 FOFST Line offset value RW 0x0
This bit field is latched by the VS sync pulse.
0x0: +1 line
0x1: +2 lines
0x2: +3 lines
0x3: +4 lines
11:9 LOFST0 Line offset values of even lines and even fields RW 0x0
(field id = 0).
This bit field is latched by the VS sync pulse.
0x0: +1 line
0x1: +2 lines
0x2: +3 lines
0x3: +4 lines
0x4: -1 line
0x5: -2 lines
0x6: -3 lines
0x7: -4 lines
8:6 LOFST1 Line offset values of odd lines and even fields RW 0x0
(field id = 0).
This bit field is latched by the VS sync pulse.
0x0: +1 line
0x1: +2 lines
0x2: +3 lines
0x3: +4 lines
0x4: -1 line
0x5: -2 lines
0x6: -3 lines
0x7: -4 lines
5:3 LOFST2 Line offset values of even lines and odd fields RW 0x0
(field id = 1).
This bit field is latched by the VS sync pulse.
0x0: +1 line
0x1: +2 lines
0x2: +3 lines
0x3: +4 lines
0x4: -1 line
0x5: -2 lines
0x6: -3 lines
0x7: -4 lines
1382 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated